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w78e054d/w78e052d/W78E051D data sheet 8-bit microcontroller pub lica tio n relea s e da te: oct 2 0 , 2 011 - 1 - revision a10 table of contents- 1 ? general des cription ......................................................................................................... 4 ? 2 ? features ....................................................................................................................... .......... 5 ? 3 ? parts inform ation list ..................................................................................................... 6 ? 4 ? pin config urations ............................................................................................................. 7 ? 5 ? pin descri ptions ............................................................................................................... ... 9 ? 6 ? block diagram .................................................................................................................. .. 11 ? 7 ? functiona l d escription.................................................................................................. 12 ? 7.1 ? on-chip fl ash eprom ................................................................................................ 12 ? 7.2 ? i/o ports ...................................................................................................................... .. 12 ? 7.3 ? serial i/o ..................................................................................................................... .. 12 ? 7.4 ? timers ......................................................................................................................... .. 12 ? 7.5 ? interrupts ..................................................................................................................... .. 12 ? 7.6 ? data po inters ................................................................................................................ 13 ? 7.7 ? arc h itec ture ................................................................................................................... 13 ? 7.7.1 ? alu ............................................................................................................................ .... 13 ? 7.7.2 ? accumula tor ................................................................................................................... 13 ? 7.7.3 ? b regi ster ..................................................................................................................... .. 13 ? 7.7.4 ? program stat us word ..................................................................................................... 13 ? 7.7.5 ? scratch-pa d ram ........................................................................................................... 13 ? 7.7.6 ? stack po inter .................................................................................................................. 13 ? 8 ? memory orga nization...................................................................................................... 14 ? 8.1 ? program memory (o n-c h ip flas h) ................................................................................. 14 ? 8.2 ? scrat c h-pad ram and register m a p ............................................................................ 14 ? 8.2.1 ? working regist er s .......................................................................................................... 16 ? 8.2.2 ? bit address abl e locat ions .............................................................................................. 17 ? 8.2.3 ? stack .......................................................................................................................... .... 17 ? 9 ? special functi o n registers ......................................................................................... 18 ? 9.1 ? sfr detail bit desc riptions .......................................................................................... 20 ? 10 ? instruction .................................................................................................................... ...... 35 ? 10.1 ? ins truc tion timing.......................................................................................................... 43 ? 11 ? power ma na gement .......................................................................................................... 44 ? 11.1 ? idle mode ...................................................................................................................... 44 ? 11.2 ? power down mode ....................................................................................................... 44 ? 12 ? reset cond itions ............................................................................................................... 45 ? 12.1 ? sourc e s of res e t ............................................................................................................ 45 ? 12.1.1 ? ex ternal reset .............................................................................................................. 45 ? 12.1.2 ? soft w a re reset ............................................................................................................. 45 ? 12.1.3 ? watchdog t i me r reset ................................................................................................. 45 ? http://
w78e054d/w78e052d/W78E051D data sheet - 2 - 12.2 ? res e t state ................................................................................................................... 45 ? 13 ? interrupts ..................................................................................................................... ...... 46 ? 13.1 ? interrupt sourc e s .......................................................................................................... 46 ? 13.2 ? priority level struc ture ................................................................................................. 46 ? 13.3 ? interrupt respons e time .............................................................................................. 48 ? 13.4 ? interrupt inputs .............................................................................................................. 49 ? 14 ? programmable time rs/counte r s ............................................................................... 50 ? 14.1 ? timer/counter s 0 & 1 .................................................................................................... 50 ? 14.2 ? time-bas e s e lec tion ..................................................................................................... 50 ? 14.2.1 ? mode 0 ......................................................................................................................... 50 ? 14.2.2 ? mode 1 ......................................................................................................................... 50 ? 14.2.3 ? mode 2 ......................................................................................................................... 51 ? 14.2.4 ? mode 3 ......................................................................................................................... 51 ? 14.3 ? timer/count er 2 ............................................................................................................ 52 ? 14.3.1 ? capture mode ............................................................................................................... 52 ? 14.3.2 ? auto-reload mode, counti ng up .................................................................................. 53 ? 14.3.3 ? auto-reload m ode, co unting up/do w n ......................................................................... 53 ? 14.3.4 ? baud rate gener ator mode ......................................................................................... 54 ? 15 ? watchdog timer ................................................................................................................. 55 ? 16 ? serial port .................................................................................................................... ...... 57 ? 16.1 ? mode 0 ........................................................................................................................ 57 ? 16.2 ? mode 1 ........................................................................................................................ 58 ? 16.3 ? mode 2 ........................................................................................................................ 59 ? 17 ? flash rom code boot mode sl ection........................................................................ 62 ? 18 ? isp (in-system programming) ........................................................................................ 63 ? 19 ? config bits .................................................................................................................... ....... 67 ? 20 ? electri c a l cha racteristics ......................................................................................... 69 ? 20.1 ? abs o lute maxi mum ratings .......................................................................................... 69 ? 20.2 ? dc ele c tri c al ch ara c teristics ...................................................................... 70 ? 20.3 ? ac electrical ch ara c teristics ...................................................................... 71 ? 20.3.1 ? clock input waveform .................................................................................................. 71 ? 20.3.2 ? program fetch cy cle .................................................................................................... 72 ? 20.3.3 ? data read cy cle .......................................................................................................... 72 ? 20.3.4 ? data write cy cle ........................................................................................................... 72 ? 20.3.5 ? port acce ss cy cle ........................................................................................................ 73 ? 20.3.6 ? program o peratio n ....................................................................................................... 73 ? 20.4 ? timing wa veforms ....................................................................................................... 74 ? 20.4.1 ? program fetch cy cle .................................................................................................... 74 ? 20.4.2 ? data read cy cle .......................................................................................................... 74 ? 20.4.3 ? data write cy cle ........................................................................................................... 75 ? 20.4.4 ? port acce ss cy cle ........................................................................................................ 75 ? 20.4.5 ? reset pin ac cess cy cle ............................................................................................... 76 ? 21 ? application circuits ........................................................................................................ 77 ?
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 3 - revision a10 21.1 ? external program me m o ry and cr ystal ........................................................................ 77 ? 21.2 ? expanded ex ternal data m e mory and o scill at or .......................................................... 77 ? 21.3 ? internal program memory and os cillator for e ft appli c ation ...................................... 78 ? 21.4 ? referenc e value of xtal ............................................................................................. 78 ? 22 ? applicatio n note ............................................................................................................... 79 ? 23 ? package dime nsio ns ......................................................................................................... 84 ? 23.1 ? 40-pin dip ..................................................................................................................... 84 ? 23.2 ? 44-pin plcc ................................................................................................................. 85 ? 23.3 ? 44-pin pqfp ................................................................................................................. 86 ? 23.4 ? 48-pin lqfp .................................................................................................................. 87 ? 24 ? revision hi stor y ............................................................................................................... . 88 ?
w78e054d/w78e052d/W78E051D data sheet - 4 - 1 general descrip t ion the w78e 05 4d/w78e05 2 d /w7 8e051 d serie s is an 8-bit microco ntrolle r whi c h can accomm odate a wide r freque ncy rang e with low po wer con s um pt ion. the instru ction se t for the w78e054 d/ w78e0 5 2 d / w78e0 5 1 d serie s is fully compatible with the stand ard 8052. the w78e0 5 4 d/w78e05 2 d /w7 8 e051 d se rie s contai ns 1 6 k/8k/4k bytes fla s h eprom progra mma - ble by ha rd ware write r ; a 256 byte s ra m; four 8 - bit bi-di r e c tional (p0, p1, p2, p3) an d bit-a ddre s sabl e i/o ports; an addition al 4-b it i/o port p4; three 16- bit timer/counte r s; a hardwa r e watchdo g timer and a seri al port. t hese peripherals are supported by 8 sources 4-l e vel interrupt capability. to facilitate pro- grammi ng an d verification, the flash eprom in si de the w78e05 4d/w78e05 2 d /w7 8 e051 d serie s allows the p r ogra m memo ry to be pro g r amme d and r ead elect r on ically. once the co de is confirme d, the use r ca n prote c t the co de for secu rit y . the w7 8e05 4d/w78e05 2 d /w7 8 e051 d serie s micro c ontrolle r has two powe r redu ction mod e s, idle mode a nd p o w er-d own mo de, both of which are soft ware sele cta b le. the idl e mode tu rn s o ff the proc- essor clo ck b ut allows for contin ued p eripheral ope ra tion. the po wer-do wn mod e stop s the crystal os- cillator for mi nimum power consumption . the exter nal clock can b e stoppe d at any time and in any state witho u t affecting th e pro c e s sor. the w 78e0 54d/ w 78e0 5 2d/w78e05 1 d se rie s con t ains in- system prog rammabl e (isp) 2kb ldrom for load er pr og ram, op erating voltag e from 3.3v to 5.5v. note: if the applied v dd is not stable , especially w i th long transition time of po w e r on/off, it?s recommended to appl y an external reset ic to the rst pin for improv i ng the stabilit y of s y s- tem .
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 5 - revision a10 2 feat ure s ? fully static desi gn 8-bit cmos mi cro c ontrolle r ? optional 1 2 t or 6t mod e ? 12t mod e , 12 clo c ks pe r machi ne cy cl e operation (default), spe ed up to 40 m h z/5v ? 6t mode, 6 cl ocks p er ma chine cy cle op erati on set by the writer, s peed u p to 20 mhz/5v ? wide sup p l y voltage of 2.4v to 5.5v ? tempe r atu r e grad e is (-4 0 o c~ 85 o c) ? pin and inst ructio n-set s compatible with mcs-5 1 ? 256 bytes o f on-chi p scra tchpa d ram ? 16k/8k/4k bytes ele c trically erasable/ prog ram m abl e flash eprom ? 2k bytes l d rom suppo rt isp function (refe r e n ce applicatio n note) ? 64kb prog ram memo ry addre s s sp ace ? 64kb data memory ad dress sp ace ? four 8 - bit bi -directio nal p o rts ? 8-sources, 4-l e vel interrupt capability ? one extra 4 - bit bit-ad dre s sabl e i/o port , additional int2 / int3 (available on pqfp, plcc and lqfp pa ckag e) ? thre e 16-bit timer/cou n ters ? one full dup lex serial p o rt ? watchdo g t i mer ? emi redu ction mode ? software res e t ? built-in po wer man agem ent with idle mode an d po wer d o wn mo de ? cod e prote c tion ? package s: di p40, plcc44 , pqfp44, lqfp48
w78e054d/w78e052d/W78E051D data sheet - 6 - 3 part s information list part no. ram ldrom size apro m size pa ck age tempera t ure grade 2k bytes 14k bytes w 7 8 e 05 4d dg 0 16k bytes dip-40 pin -40 o c~ 85 o c 2k bytes 14k bytes w 7 8 e 05 4d pg 0 16k bytes plcc-44 pin -40 o c~ 85 o c 2k bytes 14k bytes w 7 8 e 05 4d fg 0 16k bytes pqfp-44 pin -40 o c~ 85 o c 2k bytes 14k bytes w 7 8 e 05 4d lg 0 16k bytes lqfp-48 pin -40 o c~ 85 o c w78e0 5 2 d dg dip-40 pin -40 o c~85 o c w78e0 52 d p g plcc-4 4 pin -40 o c~85 o c w78e0 5 2 d f g pqfp-44 pin -40 o c~85 o c w78e052dlg 2k bytes 8k bytes lqfp-48 pin -40 o c~ 85 o c w78e0 5 1 d dg dip-40 pin -40 o c~85 o c w78e0 51 d p g plcc-4 4 pin -40 o c~85 o c w78e0 5 1 d f g pqfp-44 pin -40 o c~85 o c W78E051Dlg 256 bytes 2k bytes 4k bytes lqfp-48 pin -40 o c~ 85 o c table 3? 1: la d free (ro h s) parts info rmation list
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 7 - revision a10 4 pin configurations 18 6 5 4 3 2 1 44 43 42 41 40 19 20 21 22 23 24 25 26 27 28 p1.3 p1.2 p1.4 t2ex, p1.1 t2, p1.0 ad0, p0.0 int3, p4.2 ad1, p0.1 ad2, p0.2 ad3, p0.3 vdd xtal2 xtal1 vss p2.1, a9 p4.0 p2.2, a10 p2.3, a11 p2.4, a12 p2.0, a8 p3.7, rd p3.6, wr dip 40-pin
w78e054d/w78e052d/W78E051D data sheet - 8 - 8 12 37 7 10 9 11 44 43 42 41 40 39 38 36 35 34 32 33 30 31 28 29 26 27 24 25 23 13 14 15 16 17 18 19 20 21 22 p1.6 p1.5 rst p1.7 r x d, p3.0 t x d, p3.1 t 0 , p3.4 t 1 , p3.5 p1.3 p1.2 p1.4 t2ex, p1.1 t2, p1.0 ad0, p0.0 ad1, p0.1 ad2, p0.2 ad3, p0.3 vdd ale p0.7, ad7 p4.1 p0.6, ad6 p0.5, ad5 p0.4, ad4 p2.5, a13 p2.6, a14 p2.7, a15 xtal2 xtal1 vss p2 .1, a9 p4 .0 p2 .2, a10 p2 .3, a11 p2 .0, a8 pq fp 44- pin int 0, p3.2 p3.7, rd int 1, p3.3 psen ea p3.6, wr 2 1 4 3 5 6 in t2, p4. 3 int 3, p4.2 2 44 1 4 3 6 5 8 7 10 9 11 48 42 41 40 39 38 37 32 33 30 31 28 29 26 27 25 13 14 15 16 18 19 20 21 22 p2.7, a15 psen ad0, p0.0 ale ea p4.1 p0.6, ad 6 p0.5, ad 5 p2 .4, a12 p2 .3, a11 p2 .2, a10 p2 .1, a9 xtal2 p3 .7, rd p3 .6, wr xtal1 int 2, p4.3 int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 p1.6 p1.7 rst ad2, p0.3 ad2, p0.2 ad1, p0.1 p1.3 p1.4 p1.5 p1.2 p2 .0, a8 p4 .0 vss 12 17 23 24 34 35 36 46 47 43 45 p2.6, a14 p2.5, a13 nc vdd int3, p 4 .2 t 2 , p1.0 t2ex, p1.1 p0.7, ad 7 p0.4, ad 4 p3.1 p3.0 nc nc nc lq fp 48 -pi n p2.4, a12
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 9 - revision a10 5 pin des c riptions symbol type descriptions ea i external access enable: this pin forces the processor to execute out o f external rom. it should be kept high to access internal rom. the rom address and data will not be present on the bus if e a pin is high and the program coun- ter is within internal rom area. ot herwise they will be present on the bus. ps en o h program store enable: psen enables the external rom data onto the port 0 address/data bus during fetch and movc operations. when internal rom access is performed, no psen strobe signal outputs from this pin. ale o h address latch enab le: ale is used to enable the address la tch that sepa- rates the address from the data on port 0. rst i l reset: a high on this pin for two machine c y c l es while the osc illator is running resets the device. xtal1 i crystal1: this is the crystal oscill ator input. this pin may be driven by an ex- ternal clock. xtal2 o crystal2: this is the crystal oscillator output. it is the inversion of xtal1. vss i ground: ground potential vdd i power supply: supply voltage for operation. p0.0 ? p0.7 i/o d port 0: port 0 is an open-drain bi-directional i/o port. this port also provides a multiplexed low order address/data bus during accesses to external memory. p1.0 ? p1.7 i/o h port 1: po rt 1 is a bi-direction al i/o p o rt with i n ternal pull - up s. the bit s hav e alternate fun c tions which are descri bed b e low: t2 (p1.0): timer/counter 2 external count input t2ex (p1.1): timer/counter 2 reload/capture control p2.0 ? p2.7 i/o h port 2: port 2 is a bi-directional i/o port with internal pull-ups. this port also provides the upper address bits for accesses to external memory.
w78e054d/w78e052d/W78E051D data sheet - 10 - pin descripti on, contin ued symbol type descriptions p3.0 ? p3.7 i/o h port 3: po rt 3 is a bi-dire c tional i/o p o r t with inte rna l pull-u p s. all bits have al- ternate fun c tions, which are descri bed b e low: rxd (p3.0): serial port 0 input txd (p3.1): serial port 0 output int0 (p3.2) : external interrupt 0 int1 (p3.3) : external interrupt 1 t0 (p3.4) : timer 0 external input t1 (p3.5) : timer 1 external input wr (p3.6) : external data memory write strobe rd (p3.7) : external data memory read strobe p4.0 ? p4.3 i/o h port 4: another bit-addressable bidirectional i/o port p4. p4.3 and p4.2 are alternative function pins. it can be used as general i/o port or external interrupt input sources ( int2 / int3 ). * note: type i: input, o: o u tput, i/o: bi-directional , h: pull-high, l: pull-low, d: open drain. in applicatio n if mcu pi ns need ex ternal pull- up , it is recommended to a dd a pull-up resistor (10 k ) b e t w een pin and po w e r (v dd ) i n ste ad of dir ectly w i ring pin to v dd for enhancing emc.
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 11 - revision a10 6 block di agram figure 6?1 w78e054 d/w7 8e052 d/w7 8 e 051d blo c k diag ram
w78e054d/w78e052d/W78E051D data sheet - 12 - 7 functional de scription the w7 8e05 4d/w78e05 2 d /w7 8 e051 d serie s archit ec ture co nsi s ts of a core controlle r su rroun ded by various re gisters, five general pu rpo s e i/o port s , 16k/8k/4k flash eprom, 2k flash eprom for isp function, 256 bytes of ram, th ree ti mer/counte r s, and a serial port. the p r o c e s sor sup po r ts 11 1 different op -code s and refe ren c e s both a 64k prog ram addre s s sp a c e an d a 64k data storage spa c e. 7.1 on-chip flash epro m the w78e05 4d/w78e05 2 d /w7 8 e051 d serie s in clud e one 16k/8 k/4k bytes of main flash eprom for appli c atio n prog ram. 7.2 i/o ports the w78e0 5 4 d/w78e05 2 d /w7 8 e051 d se ries ha s fo ur 8 - bit po rts and o ne extra 4-bit po rt. po rt 0 can be used a s a n addre s s/da ta bus whe n external p r og ram is run n in g or external memory/devi c e is ac- ce ssed by m o vc o r mo vx instru ctio n. in these ca se s, it ha s st ron g pull - u p s a nd p u ll-d o wn s, an d doe s not ne e d any extern al pull-u ps. o t herwi se it ca n be u s ed a s a gene ral i/o port with o pen-drain circuit. port 2 is u s ed chie fly as the up per 8 - bit s of the address bus wh en po rt 0 is u s e d as a n ad - dre ss/d ata b us. it also has stro ng pull-ups an d pu ll-downs when it serves a s an add re ss b us. port1 and 3 act as i/o ports with alternate fun c tions. port 4 is only available on plcc/p q fp/lqfp packag e type. it serves a s a ge neral purpo se i/o port a s po rt 1 and po rt 3. another b i t-add re ssabl e bidirec- tional i/o port p4. p4.3 an d p4.2 are alternative function pins. it c an be use d as gene ral i/o port o r external inte rrupt input so urce s ( int2 / int3 ). 7.3 serial i/o the w78e 05 4d/w78e05 2 d /w7 8e051 d serie s have one se ri al po rt that is functionally simila r to th e seri al po rt of the original 8032 family. howeve r the se rial po rt on t he w7 8e054 d/ w7 8e052 d/ w78e0 5 1 d serie s ca n ope rate in differe nt modes in o r de r to obtain timing similarity as well. 7.4 timers timers 0, 1, and 2 ea ch consi s t of two 8-bit data reg i sters. the s e are called t l 0 and t h 0 fo r timer 0, tl1 and t h 1 for timer 1, and tl2 an d th2 for time r 2. the tco n and tmo d registe r s p r o v ide con - trol function s for timers 0 a nd 1. the t2co n regi st er provides con t rol function s for timer 2. rcap2 h and rcap2l are u s ed a s reload/ captu r e registe r s for timer 2. the ope ratio ns of timer 0 and timer 1 are the same as in the 805 1 cpu. timer 2 is a spe c ia l feature of the w78e 0 54d/ w 78e0 5 2 d/w78e05 1 d : it is a 16 -b it timer/cou nter that is conf igure d an d co ntrolled by the t2con regi ster. like timers 0 and 1, timer 2 can operate as either an external event counte r or a s an i n ternal timer, d e pendi ng on t he setting of bit c/t2 in t 2 co n. time r 2 ha s thre e operating mode s: ca pture, auto - relo ad, and bau d rate gene rato r. the clo ck sp eed at captu r e o r a uto-reloa d mode is the same as that o f timers 0 a n d 1. 7.5 interrupts the interrupt structu r e in the w 78e 054 d/w7 8e052 d/w78e05 1d i s slight ly different from th at of the stand ard 80 5 2. due to th e presen ce o f additional feature s and perip he rals, the numbe r of interrupt sou r ces an d vectors has b een increa se d. the w 78e 054 d/w7 8e0 52d/ w 78e0 5 1d provid es 8 interru pt resou r ces wit h four prio rity level, includi ng four exte rnal interrupt source s, thre e timer interru pts, seri al i/o interrupt s .
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 13 - revision a10 7.6 data pointers the d ata poi nter of w78e 054 d/w7 8e0 52d/ w 78e0 5 1d se rie s is same a s sta ndard 8 052 t hat have one 16 -bit da ta pointer (dptr). 7.7 architecture the w78e0 5 4 d/w78e05 2 d /w7 8 e051 d se ries are bas ed o n th e stan dard 8 052 d e vice. i t is built arou nd an 8 - bit alu that use s internal registe r s for tempora r y storag e and co ntrol of the periph e ral device s . it can execute the standa rd 80 5 2 instru ction set. 7.7.1 alu the alu i s the hea rt of the w78e 054 d/w78e05 2d/ w 78e0 51 d serie s . it is re spo nsi ble for the arith- metic and log i cal functio ns. it is also use d in decisio n makin g, in case of jump instru ction s , and is also use d in cal c ul ating jump ad dre s ses. th e use r ca nnot d i rectly use the alu, but the instru ction de cod er read s the op-cod e, de code s it, and seq uen ce s the d a ta throu gh t he alu and i t s asso ciate d regi sters to gene rate t he requi red result. th e alu m a inly uses the a c c whi c h i s a speci al fun c tio n re giste r (sfr) on the chip. anothe r sfr, namel y b register is also u s e d multiply and divide inst ru ctions. the alu gen erates several status si gnal s whi c h are sto r ed in the pro g ram statu s wo rd re giste r (psw). 7.7.2 accumulato r the accumul ator (acc) is the primary registe r use d in arithmetic, logical and da ta transfer op eration s in the w78e 054 d/w7 8e0 52d/ w 78e0 5 1d se rie s . since t he accu mulator is di rectly accessi b le by th e cpu, mo st of the high sp e ed instructi o n s ma ke u s e o f the acc as one argum en t. 7.7.3 b register this is a n 8-bit registe r th at is use d as the se con d a r gum ent in the mul an d div instructio n s . for all other in stru cti ons it ca n be use d simply a s a gen eral p urpo s e regi st er. 7.7.4 program st atus word this is an 8-bit sfr that is used to store the status bit s of the alu. it holds the carry flag, the auxiliary carry flag, general pu rpo s e flags, the registe r ban k select, the o v erflow flag, and the parit y flag. 7.7.5 scratch-pad ram the w7 8e05 4d/w78e05 2 d /w7 8e051 d serie s ha s a 256 byte on-chip scrat c h - p ad ram. this can be use d by the u s er for tempo r ary storage durin g prog ra m execution. a certain se ct ion of this ram is bit addressa ble, and can be di rectly add re ssed for thi s p urpo s e. 7.7.6 stack pointer the w7 8e05 4d/w78e05 2 d /w7 8e051 d serie s ha s a n 8- bit stack pointer whi c h points to the top of the stack. this sta ck re sides in the scrat c h pad ram in the w78e0 5 4 d /w78e0 5 2 d /w78e0 5 1 d . hen c e the size of the stack is lim ited by the si ze of this ram.
w78e054d/w78e052d/W78E051D data sheet - 14 - 8 memory organization the w7 8e05 4d/w78e05 2 d /w7 8 e051 d serie s se parate the memory into two s e parate s e c t ions , the program me mory and th e data mem o ry. the program memo ry is used to sto r e the in stru ction op- cod e s, while the data me m o ry is u s ed to store d a ta or for memory mappe d devi c e s . indirect addressing ram direct & indirect addressing ram sfrs direct addressing only 00 h 7fh 80 h ffh 64k bytes external data memory 14k/8k/4kb aprom ffffh 0 000h 3 fffh 3800h 2k b l drom 000 0 h 16 k b ap ro m 3 fffh 0000h or figure 8?1 m e mory map 8.1 program memory (on-chip flash) the prog ram memory on the w78e0 54d/ w 78e0 5 2 d/w78e05 1 d se rie s can be up to 16k/8k/4k bytes (2k bytes for isp f/w, sha r e with the w78e05 4d) lon g. all instru ction s are fetched for executio n from this memory area. the movc instruc t i on can a lso a c cess thi s memo ry reg ion. 8.2 scratch-pad ram and register map as mentione d before the w78e054 d/w7 8e052 d/w7 8 e 051d seri es have sepa rat e program an d data memory area s. there a r e also several special fu nct i on regi sters (sfrs) whi c h can be accessed by softwa r e. th e sfrs ca n be acce ssed only by dire ct addre ssi ng, while the on-chip ram ca n be ac- ce ssed by either di re ct or indire ct add re ssi ng.
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 15 - revision a10 indirect ram addressing direct & indirect ram addressing sfr direct addressing only 00 h 7fh 80 h ff h 256 bytes r a m and sfr data memor y spa c e figure 8?2 w78e054 d/w7 8e052 d/w7 8 e 051d ram and sfr me mory map since the scratch-pad ra m is only 256bytes it can be used only whe n data co nt ents are sm all. there are several other special purpose areas within the scratch-pad ra m. these are illustrated in next fig- ure.
w78e054d/w78e052d/W78E051D data sheet - 16 - bank 0 bank 1 bank 2 bank 3 03 02 01 00 04 05 06 07 0b 0a 09 08 0c 0d 0e 0f 13 12 11 10 14 15 16 17 1b 1a 19 18 1c 1d 1e 1f 23 22 21 20 24 25 26 27 2b 2a 29 28 2c 2d 2e 2f 33 32 31 30 34 35 36 37 3b 3a 39 38 3c 3d 3e 3f 43 42 41 40 44 45 46 47 4b 4a 49 48 4c 4d 4e 4f 53 52 51 50 54 55 56 57 5b 5a 59 58 5c 5d 5e 5f 63 62 61 60 64 65 66 67 6b 6a 69 68 6c 6d 6e 6f 73 72 71 70 74 75 76 77 7b 7a 79 78 7c 7d 7e 7f direct ram i ndire ct r a m 00h 07 h 28 h 08 h 0f h 10 h 17 h 18 h 1f h 20 h 21 h 22 h 23 h 24 h 25 h 26 h 27 h 29 h 2a h 2b h 2ch 2dh 2e h 2f h 30 h 7f h 80 h ffh figure 8?3 s c rat c h - pa d ram 8.2.1 working registers there are fou r sets of working r egi sters, each con s isti ng of eight 8- bit registe r s. these are termed as banks 0, 1, 2, and 3. individual re giste r s within these ban ks can b e di rectly a cce ssed by se pa rate in- stru ction s . th ese in dividual regi sters are named a s r0, r1, r2, r3, r4, r5, r6 and r7. ho wever, at one time th e w78e0 54 d /w78e0 52 d /w78e0 51 d serie s can wo rk with o nly o ne pa rticul ar ban k. th e ban k sele ctio n is done by setting rs1 - rs0 bits in t he psw. the r0 and r1 re gisters are used to store the address for indi re ct acce ssi ng.
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 17 - revi si on a1 0 8.2.2 bit address able locations the scrat c h - pad ram are a from location 20h to 2fh is byte as well as bit addre s sable. this mean s that a bit in this a r ea ca n be individu all y addre s sed. in addition some of the s frs are al so bit ad- dre s sable. th e instructio n decode r is a b l e to disting u i s h a bit a c ce ss from a byt e acce ss by the type of the instru ctio n itself. in the sfr area, a n y existing sfr wh ose ad dre ss e nd s in a 0 or 8 is bit addre s s- able. 8.2.3 stack the scratch - pad ram ca n be used fo r the sta ck. this a r ea i s sele cted by the stack pointer (sp), whi c h stores the add re ss of the t op of t he sta c k. wh enever a jum p , ca ll or inte rru pt is i nvoked the re - turn add re ss is placed on the stack. th ere is no rest riction a s to whe r e the st ack can b egi n in the ram. by default ho wever, the stack p o inter contai n s 07 h at re se t. the use r can then ch an ge this to any value desired. the sp will point to the last us ed value. therefore, the sp will be incremented and then ad dre s s saved onto th e sta ck. conv ersely, while poppi ng fro m the sta c k the conte nts will be read first, and then the sp is decre ased.
w78e054d/w78e052d/W78E051D data sheet - 18 - 9 spe cial function registers the w78e 05 4d/w78e05 2 d /w7 8e051 d serie s use s spec ial fu nct i on regi sters (sfrs) to control and monitor peri p heral s a nd th eir mo de s. the sfrs resi de in the reg i ster lo catio n s 80 -ffh an d are ac- ce ssed by direct add re ssin g only. some of the sfrs ar e bit ad dre s sable. thi s i s very useful in ca se s whe r e u s e r s wish to modif y a particular bit wit hout changi ng the others. t he sfrs th at are bit ad- dre s sable a r e those wh ose addre s se s end in 0 or 8. the w78e0 54d/ w 78e0 5 2d/w78e05 1 d seri es contai n all the sfrs present in the standa rd 805 2. howeve r so me additional sfrs are a dded. in some cases the unu sed bits in the origin al 8052, have been given new functio n s. the list of th e sfrs is as follows . f8 f f f0 b f 7 e8 e f e0 a c c e 7 d8 p 4 d f d0 p s w d 7 c8 t2c on t2mo d rcap2 l rcap2 h t l2 th2 cf c0 xicon sfral sfrah sfrrd sfrcn c7 b8 ip eapage chp con b f b0 p 3 i p h b 7 a8 i e a f a0 p 2 a 7 98 scon sbuf 9f 90 p 1 9 7 88 tcon tmod tl0 tl1 th0 th1 auxr wdtc 8f 80 p0 sp dpl dph p0upr pcon 87 table 9? 1: speci a l fun c tion re giste r l o catio n table note: 1. the sfrs in the colum n with dark bo rders are bit-a ddre s sabl e 2. the tabl e i s cond en sed with eig h t lo cations pe r ro w. empty locations i ndi cat e that the s e a r e n o reg- isters at these addresse s. whe n a bit or r egiste r is n o t implemente d , it will read high.
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 19 - revi si on a1 0 special f un c tion re giste r s: sy m bol d efin it i on add r ess m sb bit add r ess, sy m bol lsb r ese t b b r eg i ster f0h ( f 7) ( f 6) ( f 5) ( f 4) ( f 3) ( f 2) ( f 1) ( f 0) 000 0 0000b a cc a ccu mu la to r e 0 h (e 7 ) (e 6 ) (e 5 ) (e 4 ) (e 3 ) (e 2 ) (e 1 ) (e 0 ) 0 0 00 0000b p4 por t 4 d8h int 2 int 3 000 0 1 1 11 b p s w p ro g ra m st at u s w o rd d0 h (d7 ) cy (d6 ) ac (d5 ) f0 (d4 ) rs 1 (d3 ) rs 0 (d2 ) ov (d1 ) f1 (d0 ) p 000 0 0000 b t h 2 t 2 re g. h i gh cdh 0 0 00 0000b t l 2 t 2 re g. lo w cch 0 0 00 0000b rca p 2 h t 2 ca ptu r e lo w cb h 0 0 00 0000b r c ap2l t 2 cap t ur e hi g h c a h 000 0 0000b t 2 mod t i me r 2 mod e c9 dce n 0 0 00 0000b t 2 con t ime r 2 c o n t ro l c8 h (cf) tf 2 (ce) ex f2 (cd) rcl k (cc) tc l k (cb ) ex en 2 (ca ) tr 2 (c9 ) c/t 2 (c8 ) c p/r l2 000 0 0000 b s f rcn s f r p r o g ra m of con t rol c7 h noe nce ct rl 3 ct rl 2 ct rl 1 ct rl 0 0 0 0 0 00 0 0 b s f rrd s f r p ro g ra m of d a t a re giste r c6 h 0 0 0 0 00 0 0 b sfr ah sfr pr og r a m o f a ddr e ss hi g h by te c 5 h 000 0 0 000b sfr al sfr pr og r a m o f a ddr e ss l o w by te c 4 h 000 0 0 000b x i c o n ex ter nal i n ter r u p t co ntr o l c 0 h px 3 ex 3 ie3 it3 px 2 ex 2 ie2 it2 000 0 0 000b chp con ch ip co ntro l b f h s w r s t - - - - fboo t s l en p 000 0 0000b eapag e er ase p a g e o per ati o n mod e s beh eapg 1 eapg 0 000 0 0 000b ip inter r u p t pr ior i ty b8h ( b f) - ( be) - (b d) pt2 (b c) ps ( bb) pt1 ( ba) px 1 (b9 ) pt0 (b8 ) px 0 110 0 0000 b iph interru p t pr ior i ty hig h b7h 000 0 0 0 00 b p3 por t 3 b0h ( b7) rd (b 6 ) wr (b 5 ) t1 (b 4 ) t0 (b3 ) int 1 (b2 ) int 0 (b1 ) tx d (b0 ) rxd 111 1 1111 b ie interrup t e nabl e a8h ( af) ea ( ae) - (a d) et2 (a c) es ( ab) et1 ( aa) ex 1 (a9 ) et0 (a8 ) ex 0 010 0 0000 b p2 port 2 a0h ( a7) a15 (a6 ) a14 (a5 ) a13 (a4 ) a12 (a3 ) a11 (a2 ) a10 (a1 ) a9 (a0 ) a8 111 1 1111 b sbu f ser i al bu ffer 99h 000 0 0 0 00 b s co n s e ria l co nt ro l 9 8 h (9 f) sm 0/fe (9 e ) sm 1 (9 d) sm 2 (9 c) re n (9 b ) tb 8 (9 a ) rb 8 (9 9 ) ti (9 8 ) ri 000 0 0000 b p1 por t 1 90h ( 97) ( 96) ( 95) ( 94) (9 3 ) (9 2 ) (9 1 ) t2 e x (9 0 ) t2 111 1 1111 b w d tc w a t c hdog co ntr o l 8fh en w c l r w w i d l - - ps2 ps1 ps0 000 0 0 0 00 b a uxr a u x ilia r y 8 e h - - - - a l e o ff 0 0 0 0 0110b t h 1 t i m er hi gh 1 8d h 000 0 0 000 b t h 0 t i m er hi g h 0 8c h 000 0 0000b t l 1 t i m er l ow 1 8bh 000 0 0 000 b t l 0 t i m er l ow 0 8ah 0000 0000b t mo d t i me r mo de 8 9 h g a te c/ t m1 m0 g a te c/ t m1 m0 0 0 0 0 00 0 0 b t c o n t i me r co nt ro l 8 8 h (8 f) tf 1 (8 e ) tr 1 (8 d) tf 0 (8 c) tr 0 (8 b ) ie1 (8 a ) it1 (89 ) ie0 (8 8 ) it0 000 0 0 000 b pc on pow e r contr o l 87h sm od sm od 0 - por gf1 gf0 pd id l 001 1 0 0 00 b p 0 up r p o rt 0 p u ll up op t i on r e gist e r 8 6 h - - - - - - - p0up 0000 0001b dp h da ta po in t e r h i gh 8 3 h 0 0 0 0 00 0 0 b
w78e054d/w78e052d/W78E051D data sheet - 20 - dp l da ta po in t e r lo w 8 2 h 0 0 0 0 00 0 0 b sp stack pointer 81h 0000 0111b p0 port 0 80h (87) (86) (85) (84) (83) (82) (81) (80) 1111 1111b 9.1 sfr de tail bit de scrip tions port 0 bit: 7 6 5 4 3 2 1 0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 mnemo n ic: p0 addre s s: 80h bit name function 7-0 p0.[7:0] port 0 is an open-drain bi-directional i/o port if sfr p0upr. 0 (bit p0up) clear to ?0?, and w h e n sf r p0upr.0 (bit p0 up) set to ?1?, port 0 pins are intern all y p u ll e d -up. this port also provides a multiplexed low order address/data bus during accesses to external memory. stac k poi n ter bit: 7 6 5 4 3 2 1 0 sp.7 sp.6 sp.5 sp.4 sp.3 sp.2 sp.1 sp.0 mnemo n ic: sp addre s s: 81h bit name function 7-0 sp.[7:0] the stack pointer stores the scratc h-pad ram address where the stack begins. in other words it always points to the top of the stack. dat a poin t e r low bit: 7 6 5 4 3 2 1 0 dpl.7 dpl.6 dpl.5 dpl.4 dpl.3 dpl.2 dpl.1 dpl.0 mnemo n ic: dpl addre s s: 82h bit name function 7-0 dpl.[7:0] this is the low byte of the standard 8052 16-bit data pointer. dat a poin t e r hig h bit: 7 6 5 4 3 2 1 0 dph.7 dph.6 dph.5 dph.4 dph.3 dph.2 dph.1 dph.0 mnemo n ic: dph addre s s: 83h bit name function 7-0 dph.[7:0] this is the high byte of the standard 8052 16-bit data pointer. port 0 pull up option re gister bit: 7 6 5 4 3 2 1 0
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 21 - revi si on a1 0 - - - - - - - p0up mnemonic : p0upr address : 86h bit name functio n 0 p0up 0: port 0 pins are ope n-dra in. 1: port 0 pins are internally pulled-up. port 0 is structurally the same as port 2. po w e r control bit: 7 6 5 4 3 2 1 0 smod smod0 - por gf1 gf0 pd idl mnemo n ic: pco n addre s s: 87h bit name functio n 7 smod 1: this bit doubles the serial port baud rate in mode 1, 2, and 3 when set to 1. 6 smod 0 0: framing erro r dete ctio n disa ble. sco n .7 (sm0/ fe) bit is used as sm0 (stan- dard 8 052 fu nction ). 1: framing error detection enable. scon.7 (sm0/fe) bit is used to reflect as frame error (fe) status flag. 5 - reserved 4 por 0: cleared by softwa r e. 1: set automatically when a power-on reset has occurred. 3 gf1 general purpose user flags. 2 gf0 general purpose user flags. 1 pd 1: the cpu goes into the power down mode. in this mode, all the clocks are stopped and program execution is frozen. 0 idl 1: the cpu goes into the idle mode. in this mode, the clocks cpu clock stopped, so program execution is frozen. but the clock to the serial, timer and interrupt blocks is not stopped, and these blocks continue operating. timer contr o l bit: 7 6 5 4 3 2 1 0 t f 1 t r1 t f 0 t r0 ie1 it 1 ie0 it 0 mnemo n ic: t c o n addre s s: 88h bit name functio n 7 tf1 timer 1 overflow flag. this bit is se t when timer 1 overflows. it is cleared auto- matically when the program does a timer 1 interrupt service routine. software can also set or clear this bit. 6 tr1 timer 1 run control. this bit is set or cleared by software to turn timer/counter on or off. 5 tf0 timer 0 overflow flag. this bit is se t when timer 0 overflows. it is cleared auto- matically when the program does a timer 0 interrupt service routine. software can also set or clear this bit.
w78e054d/w78e052d/W78E051D data sheet - 22 - 4 tr0 timer 0 run control. this bit is set or cl eare d by software to turn timer/counte r on or off. 3 ie1 interrupt 1 edge detect flag: set by hardware when an edge/level is detected on 1 int . this bit is cleared by hardware when t he service routine is vectored to only if the interrupt was edge triggered. otherwise it follows the inverse of the pin. 2 it1 interrupt 1 type control. set/cleared by software to specify falling edge/ low level triggered external inputs. 1 ie0 interrupt 0 edge detect flag. set by hardware when an edge/level is detected on 0 int . this bit is cleared by hardware wh en the service routine is vectored to only if the interrupt was edge triggered. other wise it follows the inverse of the pin. 0 it0 interrupt 0 type control: set/cleared by software to specify falling edge/ low level triggered external inputs. timer mode con t rol bit: 7 6 5 4 3 2 1 0 ga t e t c / m1 m0 gate t c / m1 m0 timer1 timer0 mnemo n ic: t m od addre s s: 89h bit name function 7 gate gating control: when this bit is set, timer/counter 1 is enabled only while the 1 int pin is high and the tr1 control bit is set. when cleared, the 1 int pin has no effe ct, and timer 1 is enabled whenever tr1 control bit is set. 6 t c/ timer or counter select: when clear, timer 1 is incremented by the internal clock. when set, the timer counts falling edges on the t1 pin. 5 m1 timer 1 mode select bit 1. see table below. 4 m0 timer 1 mode select bit 0. see table below. 3 gate gating control: when this bit is set, timer/counter 0 is enabled only while the 0 int pin is high and the tr0 control bit is set. when cleared, the 0 int pin has no ef- fect, and timer 0 is enabled whenever tr0 control bit is set. 2 t c/ timer or counter select: when clear, timer 0 is incremented by the internal clock. when set, the timer counts falling edges on the t0 pin. 1 m1 timer 0 mode select bit 1. see table below. 0 m0 timer 0 mode select bit 0. see table below. m1, m0: mod e select bits: m1 m0 mode 0 0 mode 0: 13-bit timer/counter tlx serves as 5-bit pre-scale. 0 1 mode 1: 16-bit timer/counter, no pre-scale. 1 0 mode 2: 8-bit timer/counter with auto-reload from thx. 1 1 mode 3: (timer 0) tl0 is an 8-bit timer/ counter controlled by the standard timer0 control bits. th0 is an 8-bit timer only controlled by timer1 control bits. (timer 1)
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 23 - revision a10 timer/counte r 1 is sto pped . timer 0 lsb bit: 7 6 5 4 3 2 1 0 t l0.7 t l0.6 t l0.5 t l0.4 t l0.3 t l0.2 t l0.1 t l0.0 mn e m on ic : tl 0 addre s s: 8ah bit name function 7-0 tl0.[7:0] timer 0 lsb. timer 1 lsb bit: 7 6 5 4 3 2 1 0 t l1.7 t l1.6 t l1.5 t l1.4 t l1.3 t l1.2 t l1.1 t l1.0 mn e m on ic : tl 1 addre s s: 8bh bit name function 7-0 tl1.[7:0] timer 1 lsb. timer 0 msb bit: 7 6 5 4 3 2 1 0 t h 0.7 t h 0.6 t h 0.5 t h 0.4 t h 0.3 t h 0.2 t h 0.1 t h 0.0 mn e m on ic : th 0 addre s s: 8ch bit name function 7-0 th0.[7:0] timer 0 msb. timer 1 msb bit: 7 6 5 4 3 2 1 0 t h 1.7 t h 1.6 t h 1.5 t h 1.4 t h 1.3 t h 1.2 t h 1.1 t h 1.0 mn e m on ic : th 1 addre s s: 8dh bit name function 7-0 th1.[7:0] timer 1 msb. aux r bit: 7 6 5 4 3 2 1 0 - - - - - - - ale_off mnemo n ic: auxr addre s s: 8eh
w78e054d/w78e052d/W78E051D data sheet - 24 - bit name functio n 0 ale_off 1: disenable ale output 0: enable ale output wa tchdo g timer con t rol regis t er bit: 7 6 5 4 3 2 1 0 enw clrw widl - - ps2 ps1 ps0 mnemo n ic: wdtc addre s s: 8fh bit name functio n 7 enw enable watch-dog if set. 6 clrw clear watch-dog timer and pre-scalar if set. this flag will be cleared automati- cally. 5 widl if this bit is set, watch-d o g is enabled u nder idle m ode. if cleare d , watch-dog is disa bled un d e r idle mod e . default is cleare d . 2-0 ps2-0 watch-dog p r e-scala r time r sel e ct. pre - scalar i s sele cted when se t ps2 ? 0 as fo l- lows: ps2 ps1 p s 0 pr e-sc al a r s e l e ct 0 0 0 2 0 0 1 8 0 1 0 4 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 256 port 1 bit: 7 6 5 4 3 2 1 0 p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 mnemo n ic: p1 addre s s: 90h bit name function 7-0 p1.[7:0] general purpose i/o port. most instructions will read the port pins in case of a port read access, however in case of read-modi fy-write instructions, the port latch is read. serial port control bit: 7 6 5 4 3 2 1 0 sm0/f e sm1 sm2 ren t b 8 rb8 t i ri
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 25 - revision a10 mnemo n ic: sco n addre s s: 98h bit name functio n 7 sm0/fe serial port mode select bit 0 or framing error flag: the smod0 bit in pcon sfr determines whether this bit acts as sm0 or as fe. the operation of sm0 is described below. when used as fe, this bi t will be set to indicate an invalid stop bit. this bit must be manually cleared in software to clear the fe condition. 6 sm1 serial port mode select bit 1. see table below. 5 sm2 multiple processors communication. setting this bit to 1 enables the multiproces- sor communication feature in mode 2 and 3. in mode 2 or 3, if sm2 is set to 1, then ri will not be activated if the received 9th data bit (rb8) is 0. in mode 1, if sm2 = 1, then ri will not be activated if a valid stop bit was not received. in mode 0, the sm2 bit controls the serial por t clock. if set to 0, then the serial port runs at a divide by 12 clock of the osc illator. this gives compatibility with the standard 8052. when set to 1, the serial clock become divide by 4 of the oscilla- tor clock. this results in faster synchronous serial communication. 4 ren re ceive en ab le: 0: disa ble serial reception. 1: enable serial reception. 3 tb8 this is the 9th bit to be transmitted in modes 2 and 3. this bit is set and cleared by software as desired. 2 rb8 in modes 2 and 3 this is the received 9th data bit. in mode 1, if sm2 = 0, rb8 is the stop bit that was received. in mode 0 it has no function. 1 ti transmit interrupt flag: this flag is se t by hardware at the end of the 8th bit time in mode 0, or at the beginning of the st op bit in all other modes during serial transmission. this bit must be cleared by software. 0 ri receive interrupt flag: this flag is set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bits time in the other modes during serial reception. however the restrictions of sm2 apply to this bit. this bit can be cleared only by software. sm1, sm0: mode select b i ts: mode sm0 sm1 des c ription length baud ra te 0 0 0 synchronous 8 tclk divided by 4 or 12 1 0 1 asynchronous 10 variable 2 1 0 asynchronous 11 tclk divided by 32 or 64 3 1 1 asynchronous 11 variable serial data buf f er bit: 7 6 5 4 3 2 1 0 sbuf.7 sbuf.6 sbuf.5 sbuf.4 sbuf.3 sbuf.2 sbuf.1 sbuf.0 mnemonic: sbuf address: 99h
w78e054d/w78e052d/W78E051D data sheet - 26 - bit name functio n 7~0 sbuf serial data on the serial port is read from or written to this location. it actually consists of two separate internal 8-bit re gisters. one is the receive resister, and the other is the transmit buffer. any read access gets data from the receive data buffer, while write access is to the transmit data buffer. port 2 bit: 7 6 5 4 3 2 1 0 p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 mnemo n ic: p2 addre s s: a0h bit name function 7-0 p2.[7:0] port 2 is a bi-directional i/o port with inte rnal pull-ups. this port also provides the upper address bits for accesses to external memory. interrupt enable bit: 7 6 5 4 3 2 1 0 ea - et 2 es et 1 ex1 et 0 ex0 mnemonic : ie addre s s: a8h bit name function 7 ea global enable. enable/disable all interrupts. 6 - reserved 5 et2 enable timer 2 interrupt. 4 es enable serial port 0 interrupt. 3 et1 enable timer 1 interrupt. 2 ex1 enable external interrupt 1. 1 et0 enable timer 0 interrupt. 0 ex0 enable external interrupt 0. port 3 bit: 7 6 5 4 3 2 1 0 p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 mnemo n ic: p3 addre s s: b0h p3.7-0: general purpos e input/output port. mo st instructions will read the port pins in case of a port read a c ce ss, however in case of re ad-modify-write instru ction s , t he port latch is rea d . these alter- nate functio n s are d e scrib ed belo w : bit name function 7 p3.7 rd
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 27 - revision a10 6 p3.6 wr 5 p3.5 t1 4 p3.4 t0 3 p3.3 int1 2 p3.2 int0 1 p3.1 tx 0 p3.0 rx interrupt high priorit y bit: 7 6 5 4 3 2 1 0 iph.7 iph.6 iph.5 iph.4 iph.3 iph.2 iph.1 iph.0 mnemonic : iph addre s s: b7h bit name function 7 iph.7 1: interrupt high priority of int3 is highest priority level. 6 iph.6 1: interrupt high priority of int2 is highest priority level. 5 iph.5 1: interrupt high priority of timer 2 is highest priority level. 4 iph.4 1: interrupt high priority of serial port 0 is highest priority level. 3 iph.3 1: interrupt high priority of timer 1 is highest priority level. 2 iph.2 1: interrupt high priority of external interrupt 1 is highest priority level. 1 iph.1 1: interrupt high priority of timer 0 is highest priority level. 0 iph.0 1: interrupt high priority of external interrupt 0 is highest priority level. interrupt priorit y bit: 7 6 5 4 3 2 1 0 - - pt 2 ps pt 1 px1 pt 0 px0 mnemonic : ip addre s s: b8h bit name function 5 pt2 1: interrupt priority of timer 2 is higher priority level. 4 ps 1: interrupt priority of serial port 0 is higher priority level. 3 pt1 1: interrupt priority of timer 1 is higher priority level. 2 px1 1: interrupt priority of external interrupt 1 is higher priority level. 1 pt0 1: interrupt priority of timer 0 is higher priority level. 0 px0 1: interrupt priority of external interrupt 0 is higher priority level.
w78e054d/w78e052d/W78E051D data sheet - 28 - eapage erase page operation modes bit: 7 6 5 4 3 2 1 0 - - - - - - eapg1 eapg0 mnemonic : eapage address : bd bit name functio n 1 eapg1 1: to ease page1 when ease command is set. (ldrom) 0 eapg0 1: to ease page0 when ease command is set. (aprom) ;cpu clock = 12mhz/12t mode read_time equ 1 program_time equ 50 erase_time equ 5000 erase_aprom: mov eapage,#01h ;set eapage is aprom mov sfrcn,#erase_rom mov tl0,#low (65536-erase_time) mov th0,#high(65536-erase_time) setb tr0 mov chpcon,#00000011b mov eapage,#00h ;clear eapage clr tf0 clr tr0 ret erase_ldrom: mov eapage,#02h ;set eapage is ldrom mov sfrcn,#erase_rom mov tl0,#low (65536-erase_time) mov th0,#high(65536-erase_time) setb tr0 mov chpcon,#00000011b mov eapage,#00h ;clear eapage clr tf0 clr tr0 ret chip con t rol bit: 7 6 5 4 3 2 1 0 swrst - - - - - isp enp mnemonic : chpcon address : bfh bit name function
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 29 - revision a10 7 swrst when this bit is set to 1 and enp is set to 1. it will enf orce microcontroller reset to initial conditio n just like po we r o n reset. this action will re -boot the microcontroll er and start to norm a l ope ration. 1 isp the isp function select. when this bit is set to 1 and enp is set to 1. it will run isp function. 0 enp when this bit is s e t to 1 and swrst is s e t to 1. it will enforce microc ontrol- ler re set to ini t ial conditio n just like p o wer on reset. when this bit is set to 1 and isp is set to 1. it will run isp function note1: chpcon = 0x8 1 , it is software res e t note2: chpcon = 0x0 3 , isp function is enable d . extern al inte rrupt contro l bit: 7 6 5 4 3 2 1 0 px3 ex3 ie3 it3 px2 ex2 ie2 it2 mnemo n ic: xico n addre s s: c0h bit name function 7 px3 external interrupt 3 priority is higher if set this bit to 1 6 ex3 enable external interrupt 3 if set this bit to 1 5 ie3 if it3 = 1, ie3 is set/cleared automa tically by hardware when interrupt is de- tected/serviced 4 it3 external interrupt 3 is falling-edge/low- level triggered when this bit is set/cleared by software 3 px2 external interrupt 2 priority is higher if set this to 1 2 ex2 enable external interrupt 2 if set this bit to 1 1 ie2 if it2 = 1, ie2 is set/cleared automa tically by hardware when interrupt is de- tected/serviced 0 it2 external interrupt 2 is falling-edge/low- level triggered when this bit is set/cleared by software sfr progr a m of addres s lo w bit: 7 6 5 4 3 2 1 0 sf ral.7 sf ral.6 sf ral.5 sf ral.4 sf ral.3 sf ral.2 sf ral.1 sf ral.0 mn e m on ic : sf r a l ad d r ess : c 4 h bit name function 7-0 sfral.[7:0] the programming address of on-chip flash memory in programming mode. sfrfal contains the low- order byte of address. sfr progr a m of addres s high bit: 7 6 5 4 3 2 1 0
w78e054d/w78e052d/W78E051D data sheet - 30 - sfrah.7 sfrah.6 sfra h.5 sfrah.4 sfrah.3 sf rah.2 sfrah.1 sfrah.0 mnemo n ic: sfrah addre s s: c5h bit name function 7-0 sfrah.[7:0] the programming address of on-chip flash memory in programming mode. sfrfah contains the high-order byte of address. sfr progr a m for data bit: 7 6 5 4 3 2 1 0 sfrfd.7 sfrfd.6 sfrf d.5 sfrfd.4 sfrf d.3 sfrfd.2 sf rfd.1 sfrfd.0 mnemo n ic: sfrf d addre s s: c6h bit name function 7-0 sfrfd.[7:0] the programming data for on- chip flash memory in programming mode. sfr for pro gram con t ro l bit: 7 6 5 4 3 2 1 0 - oen cen ct rl3 ct rl2 ct rl1 ct rl0 mnemo n ic: sfrcn addre s s: c7h bit name function 5 oen flash eprom output enable. 4 cen flash eprom chip enable. 3-0 ctrl[3:0] ctrl[3:0]: the flash control signals mode oen cen ctrl<3 :0> sfr a h , s f r a l sfrfd f l ash stand b y 1 1 x x x rea d comp an y id 0 0 101 1 0f f h , 0f f h data out rea d devic e id high 0 0 110 0 0f f h , 0f f h data out rea d devic e id lo w 1 0 110 0 0f f h , 0f eh data out erase aprom 1 0 001 0 x x erase verif y a p rom 0 0 100 1 address i n data out program apr om 1 0 000 1 address i n data in program ver i f y aprom 0 0 101 0 address i n data out rea d aprom 0 0 000 0 address i n data out timer 2 control bit: 7 6 5 4 3 2 1 0 tf2 exf2 rclk tclk exen2 tr2 ct /2 cp rl /2
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 31 - revision a10 mnemo n ic: t 2 co n addre s s: c8h bit name functio n 7 tf2 timer 2 overflow flag: this bit is set when timer 2 overflows. it is also set when the count is equal to the capture register in down count mode. it can be set only if rclk and tclk are both 0. it is cleared only by software. software can also set or clear this bit. 6 exf2 timer 2 external flag: a negative transition on the t2ex pin (p1.1) or timer 2 overflow will cause this flag to set based on the cp r l /2 , exen2 and dcen bits. if set by a negative transition, this flag must be cleared by software. set- ting this bit in software or detection of a negative transition on t2ex pin will force a timer interrupt if enabled. 5 rclk receive clock flag: this bit determi nes the serial port 0 time-base when re- ceiving data in serial modes 1 or 3. if it is 0, then timer 1 overflow is used for baud rate generation, otherwise timer 2 over flow is used. setting this bit forces timer 2 in baud rate generator mode. 4 tclk transmit clock flag: this bit det ermines the serial port 0 time-base when transmitting data in modes 1 and 3. if it is set to 0, the timer 1 overflow is used to generate the baud rate clock otherwise timer 2 overflow is used. setting this bit forces timer 2 in baud rate generator mode. 3 exen2 timer 2 external enable. this bit enables the ca pture/rel oad function on the t2ex pin if t i mer 2 is not gene rating b aud clo c ks fo r the se rial p o rt. if this bit is 0, then the t2ex pin will be igno r ed, otherwise a negative tran sition de - tected on the t2ex pin will result in capt ure or reload. 2 tr2 timer 2 run control. this bit enables/disables the operation of timer 2. clear- ing this bit will halt the timer 2 and preserve the current count in th2, tl2. 1 ct /2 counter/timer select. this bit determi nes whether timer 2 will function as a timer or a counter. independent of this bi t, the timer will run at 2 clocks per tick when used in baud rate generator mode. 0 cp rl /2 captu r e/relo ad select. this bit deter mines wheth er the captu r e or rel oa d function will be used for timer 2. if either rclk or tclk is set, this bit will be ignored and the timer will functio n in an auto-relo ad mode followi n g each ove r - flow. if the bit is 0 then a u to-reloa d will occur wh en timer 2 ove r flo w s o r a fal- ling edge is detected on t2ex pin if exen2 = 1. if this bit is 1, then timer 2 captures will occur when a falling edge is detected on t2ex pin if exen2 = 1. timer 2 mode con t rol bit: 7 6 5 4 3 2 1 0 - - - - - - dce n mnemo n ic: t 2 mod addre s s: c9h bit name function 0 dcen down count enable: this bit, in conj unction with the t2ex pin, controls the direction that timer 2 counts in 16-bit auto-reload mode.
w78e054d/w78e052d/W78E051D data sheet - 32 - timer 2 cap t ure lsb bit: 7 6 5 4 3 2 1 0 rcap2l.7 rcap2l.6 rcap2l.5 rcap2l.4 rcap2l.3 rcap2l.2 rcap2l.1 rcap2l.0 mnemo n ic: rcap2l addre s s: cah bit name function 7-0 rcap2l.[7:0] this register is used to capture the tl2 value when a timer 2 is configured in capture mode. rcap2l is also used as the lsb of a 16-bit reload value when timer 2 is configured in auto-reload mode. timer 2 cap t ure msb bit: 7 6 5 4 3 2 1 0 rcap2h.7 rcap2h.6 rcap2h.5 rcap2h.4 rcap2h.3 rcap2h.2 rcap2h.1 rcap2h.0 mnemo n ic: rcap2h addre s s: cbh bit name function 7-0 rcap2h.[7:0] this register is used to capture the th2 value when a timer 2 is configured in capture mode. rcap2h is also used as the msb of a 16-bit reload value when timer 2 is configured in auto-reload mode. timer 2 lsb bit: 7 6 5 4 3 2 1 0 tl2.7 tl2.6 tl2.5 tl2.4 tl2.3 tl2.2 tl2.1 tl2.0 mnemo n ic: t l 2 addre s s: cch bit name function 7-0 tl2.[7:0] timer 2 lsb timer 2 msb bit: 7 6 5 4 3 2 1 0 th2.7 th2.6 th2.5 th2.4 th2.3 th2.2 th2.1 th2.0 mnemo n ic: t h 2 addre s s: cdh bit name function 7-0 th2.[7:0] timer 2 msb program sta t us word bit: 7 6 5 4 3 2 1 0 cy ac f0 rs1 rs0 ov f1 p mnemonic: psw address: d0h
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 33 - revision a10 bit name functio n 7 cy carry flag: set for an arithmetic operation which re sults in a carry being generated from the alu. it is also used as the accumulator for the bit operations. 6 ac auxiliary carry: set when the previous operation resulted in a carry from the high order nibble. 5 f0 user flag 0: the general purpose flag that can be set or cleared by the user. 4 rs1 register bank select bits: 3 rs0 register bank select bits: 2 ov overflow flag: set when a carry was generated from the seventh bit but not from the 8 th bit as a result of the previous operation, or vice-versa. 1 f1 user fla g 1: the general purpose flag that can be set or cleared by the user by software. 0 p parity flag: set/cleared by hardware to indicate odd/ even number of 1?s in the accumulator. port 4 bit: 7 6 5 4 3 2 1 0 - - - - p4.3 p4.2 p4.1 p4.0 mnemonic: p4 address: d8h another bit-addressable port p4 is also available and only 4 bits (p4<3:0>) can be used. this port ad- dress is located at 0d8h with the same function as that of port p1, except the p4.3 and p4.2 are alter- native function pins. it can be used as general i/o pins or external interrupt input sources ( int2 , int3 ). accumulator bit: 7 6 5 4 3 2 1 0 acc.7 acc.6 acc.5 acc.4 acc.3 acc.2 acc.1 acc.0 mnemo n ic: acc addre s s: e0h bit name function 7-0 acc the a or acc register is the standard 8052 accumulator. b regi ster bit: 7 6 5 4 3 2 1 0 b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 mnemo n ic: b ad d r ess : f 0 h bit name function
w78e054d/w78e052d/W78E051D data sheet - 34 - 7-0 b the b regi ste r is the sta n d a rd 80 52 r egi ster that serv es a s a se co nd accum ulat or.
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 35 - revision a10 10 instruction the w78e0 5 4 d/w78e05 2 d /w7 8 e051 d se rie s exe c u t e all the in struction s of th e stand ard 80 52 fam- ily. the opera t ions of the s e instru ction s , as well as th eir effect s on flag and stat u s bits, are ex actly the same. op-c ode hex code b y tes w 7 8 e 05 4d /w 7 8 e 05 2d /w 7 8 e 05 1d series clo ck c y c l es nop 00 1 12 add a, r0 28 1 12 add a, r1 29 1 12 add a, r2 2a 1 12 add a, r3 2b 1 12 add a, r4 2c 1 12 add a, r5 2d 1 12 add a, r6 2e 1 12 add a, r7 2f 1 12 add a, @r0 26 1 12 add a, @r1 27 1 12 add a, dire ct 25 2 12 add a, #data 24 2 12 addc a, r0 38 1 12 addc a, r1 39 1 12 addc a, r2 3a 1 12 addc a, r3 3b 1 12 addc a, r4 3c 1 12 addc a, r5 3d 1 12 addc a, r6 3e 1 12 addc a, r7 3f 1 12 addc a, @r0 36 1 12 addc a, @r1 37 1 12 addc a, dire ct 35 2 12 addc a, #da ta 34 2 12 subb a, r0 98 1 12 subb a, r1 99 1 12 subb a, r2 9a 1 12 subb a, r3 9b 1 12
w78e054d/w78e052d/W78E051D data sheet - 36 - op-c ode hex code b y tes w 7 8 e 05 4d /w 7 8 e 05 2d /w 7 8 e 05 1d series clo ck c y c l es subb a, r4 9c 1 12 subb a, r5 9d 1 12 subb a, r6 9e 1 12 subb a, r7 9f 1 12 subb a, @r0 96 1 12 subb a, @r1 97 1 12 subb a, direct 95 2 12 subb a, #data 94 2 12 inc a 04 1 12 inc r0 08 1 12 inc r1 09 1 12 inc r2 0a 1 12 inc r3 0b 1 12 inc r4 0c 1 12 inc r5 0d 1 12 inc r6 0e 1 12 inc r7 0f 1 12 inc @r0 06 1 12 inc @r1 07 1 12 inc direct 05 2 12 inc dpt r a3 1 24 dec a 14 1 12 dec r0 18 1 12 dec r1 19 1 12 dec r2 1a 1 12 dec r3 1b 1 12 dec r4 1c 1 12 dec r5 1d 1 12 dec r6 1e 1 12 dec r7 1f 1 12 dec @r0 16 1 12 dec @r1 17 1 12 dec di re ct 15 2 12
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 37 - revision a10 op-c ode hex code b y tes w 7 8 e 05 4d /w 7 8 e 05 2d /w 7 8 e 05 1d series clo ck c y c l es mul ab a4 1 48 div ab 84 1 48 da a d4 1 12 anl a, r0 58 1 12 anl a, r1 59 1 12 anl a, r2 5a 1 12 anl a, r3 5b 1 12 anl a, r4 5c 1 12 anl a, r5 5d 1 12 anl a, r6 5e 1 12 anl a, r7 5f 1 12 anl a, @r0 56 1 12 anl a, @r1 57 1 12 anl a, direct 55 2 12 anl a, #data 54 2 12 anl direct, a 52 2 12 anl direct, # data 53 3 24 orl a, r0 48 1 12 orl a, r1 49 1 12 orl a, r2 4a 1 12 orl a, r3 4b 1 12 orl a, r4 4c 1 12 orl a, r5 4d 1 12 orl a, r6 4e 1 12 orl a, r7 4f 1 12 orl a, @r0 46 1 12 orl a, @r1 47 1 12 orl a, dire ct 45 2 12 orl a, #data 44 2 12 orl di re ct, a 42 2 12 orl di re ct, #data 43 3 24 xrl a, r0 68 1 12
w78e054d/w78e052d/W78E051D data sheet - 38 - op-c ode hex code b y tes w 7 8 e 05 4d /w 7 8 e 05 2d /w 7 8 e 05 1d series clo ck c y c l es xrl a, r1 69 1 12 xrl a, r2 6a 1 12 xrl a, r3 6b 1 12 xrl a, r4 6c 1 12 xrl a, r5 6d 1 12 xrl a, r6 6e 1 12 xrl a, r7 6f 1 12 xrl a, @r0 66 1 12 xrl a, @r1 67 1 12 xrl a, direct 65 2 12 xrl a, #data 64 2 12 xrl direct, a 62 2 12 xrl direct, # data 63 3 24 cl r a e4 1 12 cpl a f4 1 12 rl a 23 1 12 rl c a 33 1 12 rr a 03 1 12 rrc a 13 1 12 swap a c4 1 12 mov a, r0 e8 1 12 mov a, r1 e9 1 12 mov a, r2 ea 1 12 mov a, r3 eb 1 12 mov a, r4 ec 1 12 mov a, r5 ed 1 12 mov a, r6 ee 1 12 mov a, r7 ef 1 12 mov a, @ r 0 e6 1 12 mov a, @ r 1 e7 1 12 mov a, direct e5 2 12 mov a, #data 74 2 12 mov r0, a f8 1 12
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 39 - revision a10 op-c ode hex code b y tes w 7 8 e 05 4d /w 7 8 e 05 2d /w 7 8 e 05 1d series clo ck c y c l es mov r1, a f9 1 12 mov r2, a fa 1 12 mov r3, a fb 1 12 mov r4, a fc 1 12 mov r5, a fd 1 12 mov r6, a fe 1 12 mov r7, a ff 1 12 mov r0, dire ct a8 2 24 mov r1, dire ct a9 2 24 mov r2, dire ct aa 2 24 mov r3, dire ct ab 2 24 mov r4, dire ct ac 2 24 mov r5, dire ct ad 2 24 mov r6, dire ct ae 2 24 mov r7, dire ct af 2 24 mov r0, #da ta 78 2 12 mov r1, #da ta 79 2 12 mov r2, #da ta 7a 2 12 mov r3, #da ta 7b 2 12 mov r4, #da ta 7c 2 12 mov r5, #da ta 7d 2 12 mov r6, #da ta 7e 2 12 mov r7, #da ta 7f 2 12 mov @r0, a f6 1 12 mov @r1, a f7 1 12 mov @r0, d irect a6 2 24 mov @r1, d irect a7 2 24 mov @r0, # data 76 2 12 mov @r1, # data 77 2 12 mov dire ct, a f5 2 12 mov dire ct, r0 88 2 24 mov dire ct, r1 89 2 24
w78e054d/w78e052d/W78E051D data sheet - 40 - op-c ode hex code b y tes w 7 8 e 05 4d /w 7 8 e 05 2d /w 7 8 e 05 1d series clo ck c y c l es mov dire ct, r2 8a 2 24 mov dire ct, r3 8b 2 24 mov dire ct, r4 8c 2 24 mov dire ct, r5 8d 2 24 mov dire ct, r6 8e 2 24 mov dire ct, r7 8f 2 24 mov dire ct, @r0 86 2 24 mov dire ct, @r1 87 2 24 mov dire ct, direct 85 3 24 mov dire ct, #data 75 3 24 mov dptr, #data 16 90 3 24 movc a, @a+dpt r 93 1 24 movc a, @a+pc 83 1 24 movx a, @ r 0 e2 1 24 movx a, @ r 1 e3 1 24 movx a, @ d ptr e0 1 24 movx @r0, a f2 1 24 movx @r1, a f3 1 24 movx @ d p tr, a f0 1 24 push direct c0 2 24 pop dire ct d0 2 24 xch a, r0 c8 1 12 xch a, r1 c9 1 12 xch a, r2 ca 1 12 xch a, r3 cb 1 12 xch a, r4 cc 1 12 xch a, r5 cd 1 12 xch a, r6 ce 1 12 xch a, r7 cf 1 12 xch a, @ r 0 c6 1 12 xch a, @ r 1 c7 1 12 xchd a, @r0 d6 1 12 xchd a, @r1 d7 1 12
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 41 - revision a10 op-c ode hex code b y tes w 7 8 e 05 4d /w 7 8 e 05 2d /w 7 8 e 05 1d series clo ck c y c l es xch a, dire ct c5 2 24 cl r c c3 1 12 cl r bit c2 2 12 setb c d3 1 12 setb bit d2 2 12 cpl c b3 1 12 cpl bit b2 2 12 anl c, bit 82 2 24 anl c, /bit b0 2 24 orl c, bit 72 2 24 orl c, /bit a0 2 24 mov c, bit a2 2 12 mov bit, c 92 2 24 acall addr11 71, 91, b1, 11, 31, 51, d1, f1 2 24 lcall a dd r 1 6 12 3 24 ret 22 1 24 reti 32 1 24 ajmp addr11 01, 21, 41, 61, 81, a1, c1, e1 2 24 ljmp ad dr1 6 02 3 24 jmp @a +dp t r 73 1 24 sjmp rel 80 2 24 jz rel 60 2 24 jnz rel 70 2 24 jc rel 40 2 24 jnc rel 50 2 24 jb bit, rel 20 3 24 jnb bit, rel 30 3 24 jbc bit, rel 10 3 24 cjne a, dire ct, rel b5 3 24 cjne a, #data, rel b4 3 24
w78e054d/w78e052d/W78E051D data sheet - 42 - op-c ode hex code b y tes w 7 8 e 05 4d /w 7 8 e 05 2d /w 7 8 e 05 1d series clo ck c y c l es cjne @r0, #data, rel b6 3 24 cjne @r1, #data, rel b7 3 24 cjne r0, #d ata, rel b8 3 24 cjne r1, #d ata, rel b9 3 24 cjne r2, #d ata, rel ba 3 24 cjne r3, #d ata, rel bb 3 24 cjne r4, #d ata, rel bc 3 24 cjne r5, #d ata, rel bd 3 24 cjne r6, #d ata, rel be 3 24 cjne r7, #d ata, rel bf 3 24 dj nz r 0, rel d8 2 24 dj nz r 1, rel d9 2 24 dj nz r 5, rel dd 2 24 dj nz r 2, rel da 2 24 dj nz r 3, rel db 2 24 dj nz r 4, rel dc 2 24 dj nz r 6, rel de 2 24 dj nz r 7, rel df 2 24 djnz di re ct, rel d5 3 24 table 10 -1: instru ction set for w78e0 5 4 d /w7 8 e052 d/w78e05 1d
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 43 - revision a10 10.1 instruction timing a machi ne cycle con s ist s of a se que nce of 6 state s , numbe re d s1 throu gh s6 . each state t i me last s for two oscill ator periods. thus a m achi ne cy cle take s 12 oscillato r periods or 1us if the oscil lator fre- quen cy is 12 mhz. each state i s divided into a pha s e 1 ha lf and a ph as e 2 h a lf. the fetch/execute seq uen ce s i n state s and p ha s e s for vari ou s ki n ds of in structi ons. normally two p r og ram fetche s a r e g enerated d uri ng ea ch machi ne cycl e, even if the instru ct ion b e ing exe c ute d doe sn?t re q u ir e it. if the instru ction be ing exe- cuted d oe s n? t need mo re code bytes, the cpu si mp ly ignores the extra fetch, and the program cou nter is no t increme nted . execution of a one-cy cl e instru ction b e gins du ring s t ate 1 of the machi ne cycle, wh en the opco de is latche d into the instructi on regi ster. a secon d fetch occu rs du ring s4 o f the same m a chin e cycl e. execution is compl ete at the end of sta t e 6 of this machi ne cy cle. the movx in stru ction s take two ma chin e cycle s to ex ecute. no p r o gram fet c h is gene rated du ring th e se con d cy cle of a mov x inst ru ct ion. this i s the only time p r og ram fetch e s a r e ski pp ed. the fetch/execute sequ en ce for movx instru ction s . the fetch/exe c ute se que nces are the sa me whethe r the program memory is internal o r external to the chip. executi on times do n ot depen d on wheth er the program me mory is intern al or extern al. the signal s a nd timing inv olved in p r og ram fetche s when the p r og ram memo ry i s extern al. if program memory is external, then the progr am memory read strobe psen is normally activated twice per ma- chine cycle. if an access to external data memory occurs, tw o psen pulse are skipped, because the address and data bus are being used for the data memory acce ss. note that a data memory bus cy- cle takes twi c e as mu ch ti me as a prog ram mem o ry bus cycle.
w78e054d/w78e052d/W78E051D data sheet - 44 - 11 power manageme n t the w7 8e05 4d/w78e05 2 d /w7 8 e051 d has several featur e s that help the u s er to control th e power con s um ption of the device. the p o wer saved f eatu r e s have ba si cal l y the powe r down m o de an d the idle mod e of operatio n . 11.1 idle mode the u s e r can put the devi c e into idle mo de by writing 1 to the bit p c on.0. the ins t ruct ion that s e ts the idle bit is the last instru ction t hat will be executed b efore the dev ice goe s into idle mode. in the idl e mode, the cl ock to the cpu is halt ed, but not to th e interru pt, timer, wat c hd og timer and serial po rt blocks. this forces the cp u state to be frozen; t he program co u nter, the stack pointer, the program status word, the accum ul ator a nd the other regi ste r s hol d thei r contents. t he port pi ns hold the logi - cal states th e y had at the time idle was activated. th e idle mod e can be te rmina t ed in two wa ys. since the interrupt controller is still acti ve, the activation of any enabled i n te rrupt can wake up the processor. this will a u to matically clea r the idle bit, terminate th e idle mo de, and th e inte rru pt service routin e (isr) will be executed. after the isr, execution of the program wil l c ontinue from the instruct ion whi c h put the device into idle mode. the idle m od e ca n al so be exited by acti vating the re set. the device ca n put into reset eithe r b y apply- ing a high on the external rst pin, a powe r on re se t condition o r a watch dog timer re set. the exter- nal re set pin has to be hel d high for at l east two m achine cy cle s i.e. 24 clo ck p eriod s to be reco gni zed as a vali d re set. in the reset con d ition t he prog ra m counter i s re se t to 0000h an d all the sf rs are set to the re set condition. sin c e the clo c k is alrea d y ru n ni ng there is n o delay an d e x ecution start s imme - diately. 11.2 po w e r do w n mode the devi c e can be put int o powe r do wn mode by writ ing 1 to bit pcon. 1 . the instru ction th at doe s this will be the last instruct ion to be executed before the device goes into p o wer down mode. in the powe r down mode, all the clo c ks are sto pped an d the device come s to a halt. all activity is completely stopp ed and the powe r co nsum ption is redu ce d to the lowe st possible value. t he port pin s output the values held by their respective sfrs . the w78e05 4d/w78e05 2 d /w7 8 e051 d will exit the powe r do wn mode with a reset or by an external interrupt pin e nable d as l e vel dete c ts. an external re se t can b e used to exit the power do wn sta t e. the high o n rst pin termi nate s the po we r do wn mo de, and resta r ts t he cl ock. th e prog ram exe c ution will resta r t fro m 0 000h. in th e powe r do wn mode, the clo ck i s stop ped , so the wat c hdog tim er cannot b e use d to provi de the re set to exit power down mode. the w7 8e05 4d/w78e05 2 d /w7 8e051 d can be wo ke n fr om the powe r do wn mode by forci ng an ex- ternal interru p t pin activated, provided the corr esp ondin g interrupt is enable d, while the global en - able(ea ) bit is set and the external input has been set to a level detect mode. if these con d itions are met, then the high level on the external pin re -sta rts t he oscillato r. then d e vice execute s the interrupt servi c e routin e for the corresp ondi ng external inte rru pt. after the interrupt se rvic e ro utine is compl eted, the prog ram executio n return s to the instru ction a fter one whi c h p u t the device into powe r down mo de and continu e s from the r e.
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 45 - revision a10 12 res e t conditions the user ha s several hard w are relate d option s for placin g the w7 8e054 d/w7 8 e 052d/ w 78e 051 d into reset conditio n . in gen eral, most regi ster bits g o to the i r re set val ue irre sp ective o f the re set co ndition , but there are a few flags whose state depend s on the so u r ce of reset. the user can u s e these flags to determi ne the cau s e of re set using software. 12.1 source s of rese t 12.1.1 external re set the device continuo usly sample s t he rst pin at state s5p2 of e v ery machine cycle. there f ore the rst pin must be held for at least 2 machin e cycle s (24 clo c k cycles) to en sure detection o f a valid rst hig h . th e re set circuit r y then synch r ono usly a ppl ies the intern al re set sign a l. thus th e re set is a synchro nou s operation an d requi re s the clock to be runni ng to ca use an external re set. for more tim- ing inform atio n, please refe ren c e the cha r acte r 21.4.5 (page 7 7 ). once the dev ice is in re set conditio n, it will rem ain so as lon g as rst is 1. even after rst is dea cti- vated, the de vice will conti nue to be in r e set st ate for up to two machi ne cycle s , and then begin pro- gram exe c uti on from 00 00 h. there i s no flag as soci ated with the e x ternal re set con d ition. 12.1.2 soft w a re re set the w7 8e05 4d/w78e05 2 d /w7 8 e051 d offers a software re set to swit ch ba ck to the aprom. setting chp co n bits 0, 1 and 7 to logic-1 creates softwar e reset to reset the cpu to start aprom code . note: software res e t only ldrom jump to apr om, aprom can?t s o ftware reset to ldrom. 12.1.3 watchdog timer reset the watchdo g timer i s a free ru nnin g timer with p r o g ramm able ti me-o ut interv als. th e u s er can cle a r the wat c hd og timer at any time, cau s ing it to rest a r t the count. wh en the time -o ut interval is rea c he d an interrupt fl ag is set. if the watc h dog reset is e na bled an d the watchdo g timer is not cle a r ed, the watchdo g timer will g ene ra te a re set. th is pla c e s the device into th e re set condit i on. the rese t condi - tion is maintained by hard w are for two machi ne cycl es. once the reset is remo ved the device will be- gin execution from 0000 h. 12.2 r e se t state most of the sfrs and regi sters on t he d e vice will go t o the same condition in th e reset state. the pro - gram cou nte r is forced to 0000 h and i s held there a s long as th e reset conditio n is appli ed. ho wever, the reset state does not affect t he on-chip ram. the data in the ra m will be preserved during the re- set. ho weve r, the stack po inter is reset to 07h, and th erefo r e the st ack co ntents will be lo st. the ram contents will be lost if the vdd falls bel o w approxim a tely 2v, as this is the minimum voltage level re- quire d for the ram to operate norm a lly. therefore aft e r a first time powe r on re set the ram conte n ts will be indete r minate. du ri ng a powe r fail conditio n , if the power falls belo w 2v, the ram contents are los t. after a reset most sfrs a r e cl eared. interru pts an d timers are di sabl ed. the watchdo g timer is di s- abled if the reset sou r ce wa s a por. the po rt sfrs h as 0 ffh written into them whi c h p uts the po rt pins in a hi gh state.
w78e054d/w78e052d/W78E051D data sheet - 46 - 13 interrup ts the w7 8e05 4d/w78e05 2 d /w7 8 e051 d has a 4 priority level interru pt stru cture with 8 i nterrupt sou r ces. ea ch of the interrupt source s has a n indi vi dual pri o rity bit, flag, interrupt vecto r a nd ena ble bit. in addition, the interru pts ca n be gl obally enabl e d or disable d . 13.1 interrupt s ources the external interru pts int0 and int1 can be either edge triggered or level triggered, depending on bits it0 and it1. the bits ie0 and ie1 in the tcon register are the flags which are checked to gener- ate the interrupt. in the edge triggered mode, the in tx inputs are sampled in every machine cycle. if the sample is high in one cycle and low in the nex t, then a high to low transition is detected and the interrupts request flag iex in tcon o is set. the flag bit requests the interrupt. since the external in- terrupts are sampled every machine cycle, they hav e to be held high or low for at least one complete machine cycle. the iex flag is automatically cleared when the service routine is called. if the level trig- gered mode is selected, then the reque sting source has to hold the pin lo w till the interrupt is serviced. the iex flag will not be cleared by the hardware on entering the service r outine. if the interrupt contin- ues to be held low even after the service routine is completed, then the processor may acknowledge another interrupt request from the same s ource. note that the external interrupts int2 and int3 . by default, the in dividual inte rrupt flag corre s po ndin g to e x ternal inte rru p t 2 to 3 m u st be clea red m anually by s o ftware. the time r 0 and 1 inte rru p ts are ge ne rated by the t f0 and tf1 fl ags. th ese flags are set b y the over- flow in the timer 0 and ti mer 1. the tf0 and tf1 flags are auto m atically clea red by the hard w a r e whe n the tim er inte rru pt is servi c ed. t h e timer 2 in t errupt is gen erated by a lo gical or of the tf2 a nd the exf2 flags. these flags are set by overflow or ca pture/reloa d events in the timer 2 opera t ion. the hard w a r e d o es not clea r these flags when a time r 2 in terru pt is e x ecuted. software ha s to resolve th e cau s e of the i n terrupt between tf2 a nd exf2 and cle a r the app ro p r iate flag. the se rial bl ock can g ene rate inte rru pts on re ceptio n or tran smission. t here a r e two interru p t sou r c e s from the seri al block, whi c h are o btaine d by the ri and ti bits in the sco n sf r, the s e bits are no t automatically cleared by the hardw are, and the user will have to cl ear these bits using software. all the bits that generate i n terrupts can be set or re set by hardwa r e, and there b y software i n itiated in- terru pts can be gene rate d . each of the individual in terrupts can b e enable d or disa bled by setting or clea ring a bit in the ie sfr. ie also h a s a gl obal e n able/di sable bit ea, which can be cl ea red to di s- able all the in terru pts, at once. s our ce v e ctor a d d re ss s ource v e ctor a d d re ss external interrupt 0 0003 h timer 0 ove r flow 000bh external interrupt 1 0013 h timer 1 ove r flow 001bh serial port 0023 h timer 2 ove r flow 002bh external interrupt 2 0033 h external interrupt 3 003bh table 13 ?1 w78e0 5 4 d /w78e0 5 2 d /w78e0 5 1 d interrupt vecto r table 13.2 priority le vel struc tu r e there are 4 prio rity levels for the interrupts high, low. naturally, a hi gher priority interrupt cannot be interrupted by a lower priority interrupt. however th ere exists a pre-defined hierarchy amongst the in- terrupts themselves. this hierarchy comes into play when the interrupt controller has to resolve simul- taneous requests having the same priority level. this hierarchy is defined as shown on table.
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 47 - revision a10 priorit y bi ts iph ip/ xicon.7/ xicon.3 interrupt priority level 0 0 level 0 (lowest priority) 0 1 level 1 1 0 level 2 1 1 level 3 (highest priority) the interrupt flags are sa mpled every machi ne cycl e. in the sam e machin e cycle, the samp led inter- rupts a r e poll ed and their prio rity is resolved. if certa i n condition s are met then the hard w are will exe - cute an internally generated lcal l instru ction whi c h will vecto r the proce s s to the approp riate inter- rupt vecto r ad dre ss. th e co nditi on s for g enerating the lcall a r e; 1. an interrup t of equal or h igher p r io rity is not cu rrent l y being se rviced. 2. the cu rren t polling cycl e is the last m achi ne cy cle of the instru ct ion cu rrently being exe c ut ed. 3. the cu rren t instru ction d oes n o t involve a write to ie, ip, iph, xicon registe r s and is n o t a reti. if any of these condition s are not met, then the lc a ll will not be generate d. the polling cy cle is re- peated every machi ne cycl e, with the interrupts sampl ed in the sam e machin e cycle. if an interrupt flag is active in one cycle but not resp ond e d to, and is n o t active when the above con d ition s are met, the denie d interru p t will not be servi c ed. t h i s me an s that active inte rru pts a r e n o t re membe r ed; e v ery poll- ing cycl e is n ew. the pro c e s so r respon ds to a valid interrupt by ex ecuting an lcal l instru ction to the approp riate ser- vice ro utine. this may o r may not clea r the flag whi c h cau s e d the interrupt. in case of tim e r i n terrupts, the tf0 or tf1 flags are cl eare d by hardwa r e wh ene ver the proces sor vecto r s to the approp riate timer servi c e routin e. in case of external interru pt, /in t0 a nd /int1, the flags are cle a red only if they are edge trigg e re d. in case of serial interru p ts, the flags are not clea red by hardwa r e. in the case of time r 2 interrupt, the flags are n o t cleared by hard w a r e. th e hard w a r e l c all be have s exactly like the soft- ware lca ll i nstru ction. th is instructio n save s t he pro gram cou nter content s ont o the stack, b ut does not save the program status wo rd psw. the pc is reloade d with the vector address of that interrupt whi c h ca used the lcall. these add re ss of vector for the different sou r ces a r e a s sho w n on t he belo w table. the vector table is not evenly space d ; this is to accommod ate future expan sion s to the device family. execution co ntinue s from the vect ored address till a n reti instru cti on is executed. on exe c ution of the reti instructio n the pr oce s sor p op s the stack an d loads the p c with the co ntents at the top of the st ac k. the u s er mu st t a k e care t hat the status of the st ack is restored to what is after the hard w a r e lcall, if the executio n is t o return to the inte rrupted prog ram. th e pro c e s sor d o es not notice anything if the stack contents are modified and will proceed with ex ecution from the addr ess put back into pc. note that a ret inst ru ction wo uld pe rform exactly the sam e proce s s as a re ti instruct ion, but it woul d not inform the interrupt co ntroll er that the interru pt servi c e routine i s compl eted, a nd woul d leave the controller still thinking that the servi c e rout ine is underway. each interrup t source ca n be individuall y enabled or di sa bled by setting or clea ring a bit in registers ie. the ie regi ster also co ntai ns a glo bal di sabl e bit, ea, which disabl es all interru p t s at once.
w78e054d/w78e052d/W78E051D data sheet - 48 - each interrup t source can be individuall y program me d to one of 2 prio rity levels by setting or clearin g bits in the ip regi sters. an inte rrupt se rvice ro utine in prog re ss ca n be interru pte d by a higher priority interrupt, but not by another interru pt of the same o r lower p r iority. the highe st pri o rity interrupt servi c e can not be int e rrupted by a n y other interrupt so urce. so , if two request s of different pri o rity levels are received si m u ltaneo usly, the req u e s t of highe r pri o rity level is servi c ed. if reque sts of the same p r i o rity level are re ceiv ed sim u ltaneo usly, an inte rnal p o lling seq uen ce d e ter- mines whi c h requ est is se rviced. this i s calle d the ar b i tration ra nki n g. note that the arbit r ation ranki ng is only used to resolve sim u ltaneo us request s of the same pri o rity level. table bel ow summ ari z e s the interrupt source s, flag bi ts, vector a ddre s se s, en able bits, pri o rity bits, arbitration ra nkin g, and external inte rru pt may wake up the cpu from powe r do wn mod e. sou r ce f l ag vecto r ad d ress ena b le bit i nte rrupt priority f l ag cleared by a r bitra t ion ra nk ing po w e r- do w n w akeup exter nal interr upt 0 ie0 000 3h ex0 (ie.0) iph.0, ip.0 hard w a re, soft w are 1(highest) yes t i mer 0 overfl o w t f 0 000b h et 0 (ie.1) iph.1, ip.1 hard w a re, soft w a r e 2 no external interr upt 1 ie1 001 3h ex1 (ie.2) iph.2, ip.2 hard w a re, soft w a r e 3 yes ti mer 1 overfl o w t f 1 001b h et 1 (ie.3) iph.3, ip.3 hard w a re, soft w a r e 4 no serial po rt ri + ti 002 3h es (ie.4) iph.4, ip.4 soft w a re 5 no t i mer 2 over- flo w /match tf2 002b h et 2 (ie.5) iph.5, ip.5 soft w a re 6 no exter nal interr upt 2 ie2 003 3h ex2 (x icon.2) iph.6, px2 hard w a re, soft w a r e 7 yes external interr upt 3 ie3 003b h ex3 (x icon.6) iph.7, px3 hard w a re, soft w a r e 8(lo w e st) yes table 13 ?2 s ummary of int errupt so urce s 13.3 interrupt response ti me the respon se time for ea ch inte rru pt source d epe n ds on seve ral factors, su ch as the n ature of the in- terru pt and th e instru ction unde rway. in the ca se of e x ternal interrupts int0 and int1 , th ey are sa m- pled at s5p2 of every machine cy cle an d then their correspon ding interru pt flags iex will be set or re- set. the tim er 0 an d 1 o v erflow flag s are set at c3 of the machi ne cycl e in which ove r flow has o c - curre d . these flag values are poll ed onl y in the next machi ne cy cl e. if a reque st is active and all three con dition s are met, then the hard w a r e gene rated l c all is execut ed. this lca ll itself take s four ma- chin e cy cle s to be compl eted. thu s the r e is a minimu m time of five machi ne cycl es b etwe en t he inter- rupt flag bein g set and the interrupt se rvice ro utine bei ng executed. a longer resp onse time sh ould be a n tici pated if any of the three condition s are not met. if a highe r or equal prio rity is bei ng servi c ed, the n the interrupt late ncy time o b viously d epe nd s on th e natu r e of th e
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 49 - revision a10 servi c e ro utin e currently be ing execute d . if the polling cycle is not the last mach i n e cycle of the instru c- tion being ex ecute d , then an addition al delay is intr o duced. the maximum re spon se time (i f no other interrupt is in servi c e ) occurs if the dev ice i s pe rforming a write to ie, ip, iph an d then e x ecute s a mul o r div instru ction. 13.4 interrupt in puts since the ext ernal inte rrup t pins are sa mpled on ce each ma chin e cycle, a n in put high o r lo w sh ould hold for at least one ma chine cycl e to ensure p r op e r sampli ng. if the external interrupt is hi gh for a t least on e ma chin e cycl e, and then hol d it low for at least one m ach ine cycl e. thi s is to en su re that the transitio n is seen and that interrupt req uest flag ie n is set. ien is automaticall y cleared by the cpu whe n the se rvice routin e is called. if the externa l interrupt i s l e vel-a c tivated, the ex tern al so urce mu st hold the reque st a c tive until the requ este d int e rrupt is a c tu ally gene rate d. if the exte rnal i nterrupt is still asse rt ed when the interrupt servi c e ro utin e is complete d another int errupt will be generate d. it is not necessary to clea r the inter- rupt flag ien whe n the inte rru pt is level sen s itive, it simply tracks t he input pin l e vel. if an externa l interru pt is enabl ed whe n the w7 8e054 d/w7 8e0 52d/ w 78e0 5 1d is put into powe r do wn or idle mode, the interrupt will ca use the pr o c essor to wa ke up and resume operatio n. refer to the se ction o n powe r re d uction mo de s for details.
w78e054d/w78e052d/W78E051D data sheet - 50 - 14 programmable timers/counters the w78e0 5 4d/w78e05 2 d /w7 8e051 d seri es have thre e 16 -bit prog ram m a ble timer/ cou nters. a machi ne cycl e equ als 1 2 o r 6 o scill ator perio ds, a nd i t depen ds o n 12t mo de o r 6t mod e that the user config ure d this device. 14.1 timer/cou n ters 0 & 1 w78e05 4d/ w 78e0 52 d /w78e0 51 d has two 16 -b it ti mer/cou n ters. each of these tim e r/co unte r s has two 8 bit regi sters whi c h form the 1 6 bit counti n g registe r . for timer/count e r 0 they are t h 0, the uppe r 8 bit s registe r , and tl0, the lo wer 8 bit regi st er. similarly timer/counte r 1 h a s t w o 8 bit regi s- ters, th1 and tl1. the two can be conf igure d to ope ra te eithe r as timers, co unt ing machine cycle s or as counte r s counting external input s. whe n config ured a s a "timer", the timer cou nts clo ck cy cle s . the timer clock can be pro grammed to be thou ght of as 1/1 2 of th e system clo ck. in t he " c ounter" m ode , the regi ster is in cre m ente d on the falling edg e o f the external input pin, t0 in ca se of timer 0, a nd t 1 for time r 1. the t0 and t1 input s are sam pled i n every ma ch ine cy cle at c4. if the sam pled valu e is high in one m achi ne cycle and lo w in the next, then a valid hi gh to low tra n sition o n the pin is re cog n i zed a nd the cou nt regi ster is incre- mented. sin c e it takes t w o machi ne cycl es to rec ogni ze a n egative transitio n on the pin, the m a ximum rate at which counting will take place is 1/24 of the master clo ck frequen cy. in either the "timer" o r "counte r " mo de, the cou n t regi ster will be up dated a t c3. the r efo r e, in the "ti mer" mo de, t he recog- nize d negativ e transitio n o n pin t0 and t1 can ca us e the count registe r value to be update d only in the machi ne cycle follo win g the one in whi c h the ne gative edge wa s dete c ted . the "time r " or "counte r " functio n is sel e cted by the " t c/ " bit in the t mod sp eci a l fun c tion re gister. each ti mer/ cou nter has one sele ction bit for its o w n; bit 2 of tmod sel ect s the fu nctio n for tim - er/co unte r 0 and bit 6 of tmod sele cts the fun c tion for time r/cou nter 1. in addition e ach tim - er/co unte r can be set to operate in a n y one of fo u r possibl e mo des. t he mo de sele ction i s do ne by bits m0 and m1 in the tm od sfr. 14.2 time-bas e selection w 7 8 e 05 4d /w 7 8 e 05 2d /w 7 8 e 05 1d pr o v id es us e rs w i th two m o des of ope ra tion for the ti mer. the timers can be programme d to operat e like the standard 8051 family, counti ng at the rate of 1/12 of the clock speed. this will ensure that timing loops on w78e054d/w 78e052d/W78E051D and the stan- dard 80 51 can be matched. this is the defa ult mode of opera t ion of the w 7 8 e 05 4d /w 7 8 e 05 2d /w 7 8 e 05 1d time rs . 14.2.1 mode 0 in mode 0, the timer/counter is a 13-bit counter. the 13-bit counter consists of thx (8 msb) and the five lower bits of tlx (5 lsb). the upper three bits of tlx are ignored. the timer/counter is enabled when trx is set and either gate is 0 or intx is 1. when t c / is 0, the timer/counter counts clock cycles; when t c / is 1, it count s falling e dge s on t 0 (tim er 0) or t 1 (timer 1 ) . for clock cycle s , the time ba se b e 1/12 spee d, and the falli n g edg e of th e clo c k increm ents the cou n ter. when t he 13 -bit value move s from 1ff fh to 0000 h, the timer overflo w flag tfx is set, and a n i n terrupt o c cu rs if en - abled. 14.2.2 mode 1 mode 1 is similar to mode 0 except that the counting register forms a 16-bit counter, rather than a 13- bit counter. this means that all the bits of thx and tlx are used. roll-over occurs when the timer moves from a count of 0ffffh to 0000h. the timer over flow flag tfx of the relevant timer is set and if
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 51 - revision a10 enabl ed an i n terrupt will occur. t he selectio n of the ti me-b ase in the timer m ode i s simil a r to that in mode 0. the gate functio n operates simi larly to that in mode 0. 1/12 fosc t0=p3. 4 (t 1 = p 3 .5 ) 0 1 tr0=tcon.4 (tr1=tcon.6) gat e = tm od. 3 ( gat e = tm od. 7) int0 =p3.2 (int1 =p3.3) c/t =tmod.2 (c/t =tmod.6) 07 07 tfx interrupt tl 0 (tl 1 ) th 0 (th 1) tf 0 (t f1) 4 m1 , m0 =t mo d . 1 , t m o d . 0 (m 1, m 0=t m od. 5, tmo d.4) 00 01 figure 14? 1 timer/counte r s 0 & 1 in m ode 0, 1 14.2.3 mode 2 in mode 2, the timer/co unt er is in the a uto relo ad m ode. in this m ode, tlx act s as an 8 - bit count re g- ister, whil e t h x hold s the reloa d value. whe n the tl x registe r ove r flows from f fh to 00h, the tfx bit in tco n i s set and tlx is reloa ded with the conte n ts of thx, and the co unti ng p r ocess contin ues from here. th e rel oad ope ratio n leaves t he contents of the thx registe r unchan ged. cou nting is e nable d by the trx bit and pro per set t ing of gate and intx pins. as in the other two mode s 0 and 1 mod e 2 allows counting of clock/12 or pulses on pin tn. 1/1 2 fo sc t0=p3. 4 (t 1 = p 3 .5 ) 0 1 tr 0 = tco n .4 (t r1=t c o n . 6) gat e = tm od. 3 ( gat e = tm od. 7) in t0 =p3.2 (int1 =p3.3) c/t =tmod.2 (c/t =tmod.6) 07 07 tfx interrupt tl 0 (t l1) th 0 (t h1) tf 0 (tf 1 ) figure 14? 2 timer/counte r 0 & 1 in mode 2 14.2.4 mode 3 mode 3 has d i fferent ope ra ting method s for the two timer/counte r s. for timer/counter 1, mode 3 simply freezes t he counter. ti mer/counte r 0, h o weve r, co nf igure s t l0 a n d th0 as two sep arate 8 b i t count regi sters in this mod e. the logic for this mode is sh own in the figure. tl0 u s es the timer/ cou nter 0
w78e054d/w78e052d/W78E051D data sheet - 52 - control bits t c/ , gate, tr0, int0 and tf0. the tl0 can be use d to count clock cycl es (clo ck/12 ) or 1-to-0 tra n siti ons on pin t 0 as dete r mi ned by c/t (tmod.2 ) . t h 0 is fo rced a s a clo c k cy cle co unte r (clo ck/12 ) an d take s over the use of tr1 an d tf1 from time r/counter 1. mo de 3 is u s e d in ca se s whe r e an extra 8 bit timer i s need ed. wi th timer 0 in mode 3, timer 1 can still be use d in mode s 0, 1 and 2, b u t its flexibility is somewhat limit ed. whil e it s basi c fun c tio nality is maint a ined, it no l o nger ha s control over its overflo w flag tf1 and th e enable bit tr1. time r 1 can still be u s ed a s a time r/cou nter and retain s the use of gate and int1 pin. in this co n dition it can be turned on a nd off by switchin g it out of and into its own mode 3. it can also be used as a baud rate generator for the serial port. figure 14? 3 timer/counte r mode 3 14.3 timer/cou n ter 2 timer/counte r 2 is a 1 6 bi t up/down co unter whi c h i s co nfigu r ed by the t2mo d(bit 0 ) re gister and controlled by the t2con regi ster. tim er/co unte r 2 is equip ped with a captu r e/reloa d ca p ability. as with the timer 0 and timer 1 counters, there exist s consi derable flexibility in selecting an d co ntrollin g the clock, an d in defining the ope rating mode. the clock sou r ce for timer/ cou nter 2 may be sele cted for either the external t2 pi n (c/t2 = 1) or the cr ystal oscillator, whi c h is divided by 12 (c/t2 = 0). the clo ck i s then enabl ed wh e n tr2 i s a 1, and di sable d whe n tr2 i s a 0. 14.3.1 capture mode the captu r e mode i s en ab led by setting the cp r l /2 bit in the t2con reg ister to a 1. in the capture mode, time r/ cou nter 2 se rves a s a 1 6 bit up cou nte r. wh en the counte r rolls over from 0 ffffh to 0000h, the t f2 bit is set, whi c h will generate an i n te rrupt request. if the exen2 bit is set, then a nega- tive transition of t2ex pin will cause the value in the tl2 and th2 regi ster to be captured by the rcap2l and rcap2h register s. thi s action al so causes the exf 2 bit in t2con to be set, whi c h will also g ene rate an interrupt. (r clk,tc lk, rl2 cp / )= (0,0,1)
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 53 - revision a10 figure 14? 4 16-bit ca pture mode 14.3.2 auto-reload mode, co unting up the auto-reload mode as an up counter is enabled by clearing the cp r l /2 bit in the t2 con regi ste r and cl eari ng t he dcen bit in t2mo d(bit0) re giste r . in this mode, ti mer/counte r 2 is a 16 bit u p cou n - ter. whe n the cou nter roll s over from 0 ffffh, a rel oad is g ene rated that ca u s e s the conte n ts of the rcap2 l and rcap2 h re gi sters to be rel oade d into t he tl2 and t h 2 re giste r s. the rel oad a c tion also sets the tf2 bit. if the exen2 bit is set, then a negat iv e transitio n of t2ex pin will also cau s e a reload. this ac tion als o sets the e x f2 bit in t2con. (rclk,tclk, rl2 cp / )= (0,0,0) & dcen= 0 t2=p1.0 0 1 c/t2 =t2con.1 time r2 in te rr u p t t2con.6 tr2=t2con.2 t2con.7 figure 14? 5 16-bit auto-reload mo de, cou n ting up 14.3.3 auto-reload mode, cou n ting up/do w n timer/counte r 2 will be in auto-rel oad mode as an up/do wn cou nter if cp r l /2 bit in t2con is cleared and the dcen bit in t2mod is set. in th is mode, timer/counter 2 is an up/down counter whose direction is controlled by the t2ex pin. a 1 on this pin cause the counter to count up. an over- flow while counting up will cause the counter to be re loaded with the contents of the capture registers. the next down count following the case where the contents of timer/counter equal the capture regis- ters will load a 0ffffh into timer/counter 2. in either event a reload will set the tf2 bit. a reload will also toggle the exf2 bit. however, the exf2 bit c annot generate an interrupt while in this mode.
w78e054d/w78e052d/W78E051D data sheet - 54 - (r clk,tc lk, rl2 cp / )= (0,0,0) & dcen= 1 t2=p1.0 0 1 t2ex =p1. 1 c/t2 =t2con.1 ti me r2 int e rru pt t2con.6 tr2=t2con.2 t2con.7 down c o unt ing re loa d v a l ue up counting reload value figure 14? 6 16-bit auto-reload mo de, cou n ting up 14.3.4 baud rate generator mode the bau d rat e gene rator mode is en ab led by setting ei ther the rclk or tclk bits in t2co n regi ster. while in the baud rate ge nerato r mo de , timer/co unt er 2 is a 16 b i t counte r wit h auto rel oad when the cou nt rolls ov er from 0fff fh. however, rolling over d oes not set the tf2 bit. if exen2 bit is set, then a neg ative transitio n of th e t2ex pin will set exf2 bit in the t2 co n re giste r and cau s e a n interrupt requ est. rclk+tclk=1, rl2 cp / =0 figure 14? 7 baud rate g enerator mo d e
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 55 - revision a10 15 watchdog t i mer the watchdo g timer i s a free-run ning ti mer whi c h ca n be pro gra m m ed by the u s er to serve as a sy s- tem monitor, a time-ba s e gene rato r or an event tim er. it is ba sically a set of dividers that divide the system clo c k. the divide r o utput is sele ctable an d det ermin es th e time-o ut interv al. whe n the time-out occurs a syst em re set can also be cau s ed if it is ena bled. the m ai n use of the watchdo g timer is as a system m onitor. thi s is im portant in rea l -time co ntrol appli c ation s . in ca se of po wer glitch es or ele c tro - magneti c inte rfere n ce, the pro c e s sor m a y begin to ex ecute errant code. if th is is left unche cked the entire system may crash. the watchd og time-out selection will result in different time-out values de- pendi ng on the clo ck sp eed . the wat c hd og timer will d e disa bled o n reset. in gen eral, software shoul d resta r t the watchd og timer to put it into a kno w n st at e. the co ntro l bits that sup port the watchdog tim - er are discu s sed b e lo w. enw : enable watchdo g if set. clrw : clear wat c hdog timer an d pre-scalar if set. this fl ag will be cleared automatically widl : if this bit is set, watch-dog i s e nable d unde r idle mode. if cleared, wa tchdo g is di sabled u n - der idle mo de. default is clea red. ps2, ps1, p s 0: watc hdog pre-sc alar timer selec t. pre-sc alar is selec t ed when s e t ps2 ? 0 as follows : ps2 ps1 p s 0 pre-s c alar selec t 0 0 0 2 0 0 1 8 0 1 0 4 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 256 the time-o ut perio d is obta i ned u s ing th e followin g eq uation for 12 t per ma chin e cycle: ms scalar e osc 12 1000 pr 2 1 14 ? before watchdog time -ou t occurs, the prog ram m u st clea r the 14-bit time r b y writing 1 to wdt c .6 (cl r w). after 1 is written to this bit, th e 14-bit timer, pre-scala r and this bit will be reset on the next instru ction cycle. the watchdog time r is clea red o n re set.
w78e054d/w78e052d/W78E051D data sheet - 56 - figure 15? 1 watchdo g timer block di agra m typical watch-dog time-o ut period whe n osc = 2 0 mhz ps2 ps1 ps 0 watchdo g time-out pe rio d (for 12 t per machi ne cy cl e) 0 0 0 19.66 ms 0 1 0 78.64 ms 0 0 1 39.32 ms 0 1 1 157.28 ms 1 0 0 314.57 ms 1 0 1 629.14 ms 1 1 0 1.25 s 1 1 1 2.50 s table 15 ?2 watch-dog ti me-o ut perio d for 12t pe r machi ne cy cl e, 20mhz ps2 ps1 ps 0 watchdo g time-out pe rio d (for 6t p er m achi ne cy cle) 0 0 0 9.83 ms 0 1 0 39.32 ms 0 0 1 19.66 ms 0 1 1 78.64 ms 1 0 0 157.28 ms 1 0 1 314.57ms 1 1 0 629.14 ms 1 1 1 1.250 s table 15?3 watch-dog time-out period for 6t per machine cycle, 20mhz
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 57 - revision a10 16 serial port serial po rt in this device is a full duple x port. the serial po rt is capabl e of synch r on ou s a s well a s asyn chrono u s comm uni ca tion. in synch r ono us mo de the device ge nerate s the cl ock and ope rates in a half-du plex m ode. in the a synchrono us mode, full du plex ope ratio n is availa ble. this m ean s that it can simultan eou sl y transmit an d receive data. the tr ansmit registe r and the receive buffer are both ad- dressed as s b uf special function register. however any write to sbuf will be to the transmi t regi s- ter, while a read from sbuf will be from the receiver buffer regi ster. the seri al port can operate in four different mod e s a s de scrib ed belo w . 16.1 mode 0 this mod e p r ovide s syn c hron ou s com m unication with external device s . in this mode seri a l data is transmitted and re ceived on the rxd line. txd is used to tran smit the shift clo ck. the t x d clock is provide d by the devi c e whether it i s transmitting or re ceiving. t h is mo de i s t herefo r e a h alf-dupl ex mode of se ri al comm uni cation. in this mode, 8 bits are tra n smitt ed or receive d per fram e. the lsb is transmitted/re ceived first. the baud rate is fixed at 1/ 12 of the oscill ator frequ en cy. this baud rate is determi ned b y the sm2 bit (scon.5 ) . whe n this bit is set to 0, then the se rial port runs at 1/12 of the clo ck. this a dditional facili ty of program mable bau d rate in mode 0 is the only differen c e bet wee n the stand ard 8 0 5 1 and w78e0 54d/ w 78e0 5 2 d/w78e05 1 d . the function a l block diag ra m is shown below. data e nters an d lea v es the seria l port on the rxd line. the txd lin e is u s ed to o u t put the shift clo ck. th e sh ift clock is u s ed to shift data into and o u t of this device and th e device at th e other end o f the line. any instru ction th at cau s e s a write to sbuf will sta r t the transmission. the shift clock w ill be activated and data will be shi fted out on the rxd pin till all 8 bits are tran smitted. if sm 2 = 1, then the data on rxd will app e ar 1 cl ock pe riod befo r e t he falling edge of shift clo ck on tx d. the clo ck on txd then re mains l ow fo r 2 clo c k pe rio ds, an d then goe s hig h again. if sm2 = 0, the data on rxd will appe ar 3 clo c k pe riod s bef ore the fallin g edge of shift clo ck o n txd. the clo ck o n txd th en rem ain s lo w for 6 cl oc k perio ds, an d then goe s hig h again. thi s ensu r e s that at the re ceiving end t he data on rxd line can ei ther be clo c ked o n the risin g ed ge o f the shift clo ck o n txd or latch ed wh en the txd cl ock is lo w.
w78e054d/w78e052d/W78E051D data sheet - 58 - figure 16? 1 serial po rt mode 0 the ti flag is set high in s6p2 followin g the end of tr ansmi ssion o f the last bit. the se rial po rt will re- ceive data when ren is 1 and ri is zero. the shift cl ock (txd) will be activated and the seri al port will latch d ata on the risi ng ed ge of shift cl o ck. th e external device sh ould the r efore pre s e n t dat a on the falling edge on the shift clock. t h is process continues till all the 8 bi ts have been rece ived. the ri flag is set in s6p2 following the last rising e dge of the sh ift clock on txd. this will stop reception, till the ri is cle are d by softwa r e. 16.2 mode 1 in mode 1, the full duplex asyn chrono u s mode i s used. serial co mmuni cation frame s are m ade up of 10 bits tran smitted on txd and received on rx d. the 10 bi ts co nsi s t of a start bit (0), 8 data bits (lsb first), an d a stop bit (1). on receive, the stop bit goe s i n to rb8 in th e sfr s c o n . the ba ud ra te in this mode is vari able. the serial baud can be prog ramm ed to be 1/1 6 or 1/32 of the timer 1 overflow. since the tim e r 1 ca n be set to different reloa d value s , a wide varia t ion in baud rates is p o ssib le. tran smi ssi on begin s with a write to sbuf. the serial data is b r o ug ht out on to t x d pin at s6p 2 follow- ing the first roll-ove r of divide by 16 co unter. th e ne xt bit is place d on txd pi n at s6p2 followin g the next rollover of the divide by 16 counte r . thus the transmi ssion is synchroni ze d to the divid e by 16 cou nter an d not dire ctly to the write to sbuf sig nal. after all 8 bits of data ar e transmitted, the stop bit is tran smitted . the ti flag is set in the s6p2 st ate after the stop bi t has been p u t out on txd pin. this will be at the 10th rollover of the divide by 16 counters after a write to sbuf. re ceptio n is enabl ed only if ren is high. the seri a l por t actually starts the re ceiving of serial data, with the dete c tion of a falling edge o n the rxd pin. t he 1-to -0 de tector continu ously monito rs the rxd line, samplin g it at the rate of 16 times the se lected baud rate. whe n a falling edge is det ected, the divide by 16 cou n ters is i mmediately reset. this h e l p s to align th e bit bounda ries with the rollovers of the divide by 16 co unters.
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 59 - revision a10 the 16 states of the counte r effect ively divide the bit time into 16 sli c e s . the bit d e tection i s do ne on a best of thre e basi s . the bit detector sa mples the rxd pin, at the 8th, 9th and 10th co unter states. by usin g a maj o rity 2 of 3 voting sy stem, th e bit value i s sele cted. t h is is don e to i m prove th e n o ise reje c- tion feature o f the seri al po rt. if the first bit detect ed a fter the falling edge of rx d pin is not 0, t hen this indicates a n invalid sta r t bit, and the reception is imm ediately abo rted. the serial port agai n lo oks for a falling edge i n the rxd line. if a valid start bit is det ected, then the rest of t he bits are also detected and shifted in to the sbuf. after shifting in 8 data bits, there is one more shift to do, after which the sbuf and rb8 are loade d and ri is set . however ce rtain con ditio ns must be met before the loading a nd setting of ri can be done. 1. ri must be 0 and 2. either sm2 = 0, or the re ceived stop bi t = 1. if these co ndi tions are met , then the sto p bit goes to rb8, the 8 d a ta bits go into sbuf and ri is set. otherwise the received frame may be lost. after the mi ddle of the stop bit, the receiver go es ba ck to looki ng for a 1-to-0 tran sition on the rx d pin. 1/2 1/16 tx c l o c k rx clock ti ri tx s h i ft tx s tar t rx shift l o ad s bu f smod cl ock sin d8 sbuf r ead s b u f internal data bus serial controllor clock lo a d pa r i n tx s tar t internal data bus w r i te to sb u f so u t t r a n s m i t s h i ft r e g i s t e r serial interrupt tx d rx d pa r o ut rb8 st a r t stop 0 1 bit detector 1-to-0 detector sample 1/16 0 ti m e r 1 ov e r f l o w 1 r e ce i v e s h i f t r e gi s t er 01 01 tc lk rcl k ti m e r 2 ov e r f l o w figure 16? 2 serial po rt mode 1 16.3 mode 2 this mod e uses a total of 11 bits in asynch ron o u s full-dupl ex com m unication. the function al descri p - tion is sho w n in the figure belo w . the frame con s ist s of one sta r t bit (0), 8 d a ta bits (lsb first), a pro - gramm able 9 t h bit (tb8) and a stop bit (1). the 9th bi t received is put into rb8. the baud rate is pro-
w78e054d/w78e052d/W78E051D data sheet - 60 - gramm able t o 1/32 or 1/6 4 of the oscill ator freq uen cy, which i s de termine d by the smod bit in pco n sfr. tran sm issi on begi ns with a write to sbuf. the serial dat a is broug ht out on to txd pin at s6p2 followin g the first roll-ove r of the divide by 16 count e r . the next bit is placed on txd pin at s6p2 fol- lowin g the ne xt rollover of the divide by 16 co unter. thus th e tran smissio n is synchroni zed t o the di- vide by 16 counters, and n o t directly to the write to sbuf sign al. after all 9 bits of data are transmitted, the stop bit is tran smitted. the ti flag i s set in the s 6 p2 state after the stop bi t has b een p u t out on txd pin. thi s will be at the 11th rollover of the di vide by 16 counters after a write to sbuf. reception is enable d on ly if ren is h i gh. the seri al port actual l y starts the receivin g of serial data, with the de- tection of a falling edge on the rxd pin. the 1-to -0 de tector continu ously monito rs the rxd line, sam- pling it at the rate of 16 tim e s the sele cted bau d rate. when a fallin g edge i s det ected, the div i de by 16 cou n ters is immediately reset. this hel ps to align the bit boundaries with the rollovers of th e divide by 16 co unte r s. the 16 state s of the co u n te r effectively d ivide the bit time into 16 sli c e s . the bit d e tection is done on a best of three basi s . the bit detector sa m ples the rxd pin, at the 8th, 9th and 10th coun- ter state s . by using a maj o rity 2 of 3 voting system, t he bit value is sel e cte d . this is d one to improve the noise reje ction feature of the serial p o rt. 1/2 1/16 tx clock rx clock ti ri tx shif t tx s tar t rx shift lo a d sbuf smod clock sin d8 sbuf read s b uf internal data bus serial controllor clock load parin tx s t a r t internal data bus write to sbuf so ut transmit shift register serial interrupt txd rxd pa rout rb8 start st o p 0 1 bit detector 1-to-0 detector sample 1/16 0 fo s c / 2 1 d8 tb8 receive shift register figure 16? 3 serial po rt mode 2 if the first bit detecte d after the falling edge of rxd pin, is not 0, th en this indica tes an invalid start bit, and the rece ption is imm e diately abo rte d . the serial port ag ain loo ks fo r a fallin g edge i n the rxd line. if a valid start bit is detecte d, then the re st of the bits are al so d e te cted an d shift ed into the sbuf. af- ter shifting in 9 data bits, th ere i s o ne m o re shift to d o , after whi c h the sbuf an d rb8 are lo aded an d ri is set. ho wever ce rtain conditio ns m ust be met be fore the loadi ng and settin g of ri can b e done. 1. ri must be 0 and 2. either sm2 = 0, or the re ceived stop bi t = 1.
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 61 - revision a10 if these co ndi tions are met , then the sto p bit goes to rb8, the 8 d a ta bits go into sbuf and ri is set. otherwise the received frame may be lost. after the mi ddle of the stop bit, the receiver go es ba ck to looki ng for a 1-to-0 tran sition on the rx d pin. mode 3 this mod e is similar to mode 2 in all resp ect s , ex cept that the b aud rate is p r ogra mmabl e. the use r must first initialize the seri al related sf r scon bef ore a n y co m m unication can take pla c e. this i n - volves sele cti on of the mo de and baud rate. the ti mer 1 shoul d also be initialized if modes 1 and 3 are used. in all four mode s, tran smi ssi o n is starte d b y any instruct ion that u s e s sbuf a s a d e stinatio n regi ster. re ception is initiated in mode 0 by t he condition ri = 0 and ren = 1. this will gene rate a clo ck o n the txd pin an d shift in 8 bits on the rx d pi n. reception i s initiated in the othe r mod es by the incomi ng start bit if ren = 1. the external device will start the com m unication by transmitting the start bit. figure 16? 4 serial po rt mode 3 sm0 sm1 mode type baud clo c k frame siz e start bit stop bit 9th bit functio n 0 0 0 synch. 4 or 12 t c lk s 8 bits no no non e 0 1 1 asynch. timer 1 o r 2 10 bits 1 1 non e 1 0 2 asynch. 32 or 64 tclks 11 bits 1 1 0, 1 1 1 3 asynch. timer 1 o r 2 11 bits 1 1 0, 1 table 16?5 serial ports modes
w78e054d/w78e052d/W78E051D data sheet - 62 - 17 flas h rom code boot mod e slecti on the w7 8e05 4d/w78e05 2 d /w7 8 e051 d boots from apr om prog ram (1 6k/8k/4k bytes) or ldrom prog ram (2k bytes) at po wer on reset or external re se t. boot mode select b y config bits cbs (config.2) config boot select at power-on reset and external reset. 1: boot from aprom (0x0000). 0: boot from ldrom (0x3800).
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 63 - revision a10 18 isp (in-system programming) isp is the abi lity of progra m mcu to be prog ram m ed while f/w code in ap -r om or ld-rom. (note: timer 0 for p r ogra m , era s e , read on isp mode. isp operation voltag e 3.3- 5.5v) start s e t t i n g c o nt r o l r e gi s t e r s m o v s f rcn , # 3 f h m o v sf r f d , #a b h mo v s f ral , # f fh mo v sfr a h , # f fh m o v chpco n , # 03h setting timer (about 450 us) and enable timer interrupt start timer and enter idle mode. (cpu will be wakened from idle mode by timer interrupt, then enter in-system programming mode) part 1:2kb aprom procedure of entering in-system programming mode execute the normal application program e n te r i n - s ys te m programming mode ? (conditions depend on user's application) end yes go no
w78e054d/w78e052d/W78E051D data sheet - 64 - go timer interrupt service routine: stop timer & disable interrupt end of programming end of erase operation. cpu will be wakened by timer interrupt. s etti n g t i m er an d e na b l e t i m e r interrupt for wake-up . (15 ms for erasing operation) start timer and enter idle mode. (erasing...) part 2: procedure of updating the 2kb aprom is f02k boot mode? s et t i ng er as e oper a t i on m ode : m o v e r pa ge , # 0 2 h m o v s f rcn , #22h (erase 2kb aprom isp ) pgm no yes
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 65 - revi si on a1 0 pgm read_device_id mov sfrcn,#0ch mov chpcon,#03h s e tti n g t i m e r and e n a b l e t i m e r interrupt for wake-up . (50us for program operation) re ad _vt mo v sf rc n, # 0 d h m o v sfra l , #0 1h m ov s f ra h, #0 0h mo v ch pc o n , # 0 3 h . part 2: procedure of updating the 2kb aprom end of programming ? g e t t he p a ram e ters of n e w co de (a dd r e ss an d da t a by tes ) through i/o ports, uart or other interfaces . setting control registers for programming: mov sfrah,#address_h mov sfral,#address_l mov sfrfd,#data mov sfrcn,#21h no yes re ad _com p ay_ id ov sf r cn, # 0 bh mov chpcon,#03h r ead _d i s t m o v sf rcn , # 0 e h m o v sfra l , #0 2h m ov s f ra h, #0 0h mo v ch pc o n , # 0 3 h . is c u rre nt l y i n th e f02k boot mode ? ease 14k ap programming: mov erpage,#01 mov sfrcn,#22h
w78e054d/w78e052d/W78E051D data sheet - 66 - pgm software reset cpu and re-boot from the 2kb aprom. mov chpcon,#81h hardware reset to re-boot from new 2 kb aprom. (s/w reset is invalid in f02k boot mode) s e tti n g t i m er and ena b l e ti m er interrupt for wake-up . (50us for program operation) end executing new code from address 00h in the 2kb aprom. part 2: procedure of updating the 2kb aprom end of programming ? g et the p ar am ete rs of n e w co de (addr e ss a n d d a t a byt e s ) through i/o ports, uart or other interfaces . setting control registers for programming: mov sfrah,#address_h mov sfral,#address_l mov sfrfd,#data mov sfrcn,#21h is cur r e n t l y i n th e f02k boot mode ? no yes no yes read_compay_id read_device_id read_vt read_dist ease 14k ap programming: mov erpage,#01 mov sfrcn,#22h
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 67 - revision a10 19 config bits duri ng the o n -chip fla s h eprom op eration mode, t he fla s h eprom can b e prog ramm ed and veri- fied repeate d l y . until the code insi de the flash eprom is confirmed ok, the cod e can be prote c ted. the protectio n of flash ep rom a nd tho s e op eratio ns on it are describ ed bel ow. the w78e05 4d/w78e05 2 d /w7 8 e051 d has a spe c i a l se tting re gister, the co nfig bits, which cann ot be a c cesse d in no rmal m o de. the s e cu rity regi ster can only be a c ce ssed from t he fla s h ep rom op- eration mod e . those bits of the securi ty regi ste r s can not be ch ange d on ce they have b e en p r o- gramm ed fro m high to lo w. they can o n ly be re set t h rou gh e r a s e - all op eratio n. the se curity regi ster is add re ssed in the flash e p rom operat ion mode by address #0 f fffh.
w78e054d/w78e052d/W78E051D data sheet - 68 - bit 0: lo ck b i ts 0: lock ena bl e 1: lock disabl e this bit is u s ed to prote c t the cu stome r ' s pr ogram co de in the w7 8e054 d/w7 8 e 052d/ w 78e 051 d. it may be set after the progra mmer finish e s the prog ra mming and verifies sequ e n ce. on ce these bits are set to logic 0, both the flash data and special settin g regi sters cannot be a ccessed a gain. bit 1: m ovc inhibit 0: movc inhi bit enable 1: movc inhi bit disabl e this bit is u s ed to re strict the acce ssi bl e regio n of the movc in struction. it can prevent the movc in- stru ction in e x ternal program memo ry from readin g the internal progra m co de. whe n this bit is set t o logic 0, a movc instruction in ex ternal program memory space will be able to access code only in the external m e m o ry, not in th e intern al me mory. a mo v c in stru ction in intern al p r ogra m mem o ry spa c e will always b e able to a ccess the rom data in both in ternal and e x ternal mem o ry. if this bit is logi c 1, there a r e no restri ction s on the movc in stru ction. bit 2: cbs config b oot select at powe r-o n re set an d external reset. cbs=1: boot from aprom block (defa u l t ). cbs=0: boot from ldro m block (0x38 0 0 ). bit 3: nsr ( n oise sen sit iv it y reduction) nsr=1: noi s e sensitivity red u ctio n is disa bled. nsr=0: noi s e sensitivity red u ctio n is enabl ed. bit 4: mu st b e ?1 ? bit 5: m achi n e c y cle select this bit is sel e ct mcu core , default valu e is logic 1, and the mcu core is 12t pe r instru ction. once thi s bit is set to logic 0, the mcu co re is 6 t per in stru ctio n. bit 6: mu st b e ?1 ? bit 7: cr y stal select 0 (24m hz): if system cl ock is slo w e r tha n 24mhz, pro g rammi ng ?0 ?. it can red u ce emi effect and save the power co nsum ption. 1 (40m hz): if system clo ck is fa ste r than 24mhz, programming ?1?.
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 69 - revision a10 20 electrical characte r ist i cs 20.1 absolute maximu m ratings symbol parameter min max unit dc po we r supply v dd ? v ss 2.4 5.5 v input voltage v in v ss -0.3 v dd +0. 3 v operating te mperature (w78e05 4d/ w 78e0 52 d /w78 e051d) t a -40 +85 c note: exposu r e to co nditio n s beyo nd th ose li sted un der a b solute maximum rati ngs m a y adversely af- fects the lift and relia bility of the device.
w78e054d/w78e052d/W78E051D data sheet - 70 - 20.2 dc ele c t r ic al ch ar acte r i s tics t a =-40 ~+ 85 , v dd =2.4v~5.5v, v ss =0v sy m parameter test conditi on min ty p *1 max unit v il input low vol t age (port s 0~4, /ea, xtal1, rst) 2. 4 < v dd < 5 . 5 v -0.5 0.2v dd -0.1 v v ih input high vo ltage (port s 0~4, /ea) 2. 4 < v dd < 5 . 5 v 0.2v dd +0. 9 v dd + 0.5 v v ih 1 input high vo ltage (xtal1, rst ) 2. 4 < v dd < 5 . 5 v 0.7v dd v dd + 0.5 v v ol output lo w voltage (port s 0~4, ale, /psen) v dd = 4 .5v, i ol = 12.0ma *3,*4 v dd = 2 .4v, i ol = 10ma *3,*4 0.4 v v oh1 output hig h voltage (port s 1~4) v dd = 4 .5v, i oh = -30 0 a *4 v dd = 2 .4v, i oh = -35 a *4 2.4 2.0 v v oh2 output hig h voltage (port s 0 & 2 in external bus mode, ale, /psen) v dd = 4 .5v, i oh = -8. 0 ma *4 v dd = 2 .4v, i oh = -2. 2 ma *4 2.4 2.0 v i il logi cal 0 inp u t current (port s 1~4) v dd = 5 .5v, v in =0.4v -45 -50 a i tl logi cal 1-to -0 tran sition curre n t (port s 1~4) *2 v dd = 5 .5v, v in =2.0v -510 -650 a i li input lea kag e curre n t (port 0) 0 < v in < v dd +0. 5 0.1 10 a ac tive mode *5 @12 m h z , v dd =5. 0 v @40 m h z , v dd =5. 0 v @12 m h z , v dd =3. 3 v @20 m h z , v dd =3. 3 v 9.5 16.0 3.1 3.7 ma idle mode @12 m h z , v dd =5. 0 v @40 m h z , v dd =5. 0 v @12 m h z , v dd =3. 3 v @20 m h z , v dd =3. 3 v 3.5 9.2 1.2 1.7 ma i dd powe r suppl y current powe r-d own mode <1 50 a r rst rst-pi n internal pull- down re si sto r 2.4 < v dd < 5.5v 100 225 k ? note: *1: typical value s are n o t gua rantee d. the values li sted are teste d at room temp erature an d ba sed on
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 71 - revision a10 a limited num ber of sample s. *2: pins of ports 1~4 sou r ce a transition current w hen they are bein g externally driven from 1 to 0. the tran sition current reaches its m a ximum value wh en v in is approximately 2v. *3: und er ste ady state (no n -transi ent) cond itions, i ol must be external ly limited as follows: maximum i ol per po rt pin: 20ma maximum i ol per 8 - bit port: 40ma maximum total i ol for all o u tputs: 100m a *4: if i oh exceeds the test cond ition, v oh will be lower than the listed specification. if i ol exceeds the test cond ition, v ol will be higher than the listed specifi c ation. *5: tested while cpu is kept i n reset state and ea=h, port0=h. voltage max. fre que ncy 6t/12t mo de note 4.5-5.5v 40mhz 12t 4.5-5.5v 20mhz 6t 2.4v 20mhz 12t 2.4v 10mhz 6t freq uen cy vs voltage table 20.3 ac ele c t r ic al ch ar acte r i s tics the ac spe c i f ication s are a function of the particul ar pro c e ss used to manufactu re the pa rt, the rating s of the i/o buf fers, the ca p a citive loa d , and the inter nal routing ca pacita nce. m ost of the sp ecification s can be expre s sed in terms of multiple input clock peri ods (t cp), and actual parts will usually experi- ence less tha n a 20 ns variation. 20.3.1 clock input waveform t t xtal1 f ch cl op, t cp parameter symbol min. typ. max. unit notes operating sp eed fop 0 - 40 mhz 1 clo ck period tcp 25 - - ns 2 clo ck high tch 10 - - ns 3 clo ck low tcl 10 - - ns 3 note s: 1. the clo c k may be stopp ed indefinitely in either stat e. 2. the tcp specifi cation is used as a reference in other specifications.
w78e054d/w78e052d/W78E051D data sheet - 72 - 3. there a r e no duty cycle requi rem ents on the xtal1 input. 20.3.2 program fe tch c y cle parameter symbol min. typ. max. unit notes addre s s valid to ale low taas 1 tcp - - - ns 4 addre s s hol d from ale low taah 1 tcp - - - ns 1, 4 ale low to psen low tapl 1 tcp - - - ns 4 psen low to data valid tpda - - 2 tcp ns 2 data hold after psen high tpdh 0 - 1 tcp ns 3 data float after psen high tpdz 0 - 1 tcp n s ale pulse wi dth talw 2 tcp - 2 tcp - ns 4 psen pulse width tpsw 3 tcp - 3 tcp - ns 4 note s: 1. p0.0 ? p0.7, p2.0 ? p2.7 re mains stable throug hout e n tire memo ry cycle. 2. memory access time i s 3 tcp. 3. data have been latched internally prior to psen going hig h . 4. " " (due to buffer drivin g delay and wire loadin g ) is 20 ns. 20.3.3 data r ead c y cle parameter symbol min. typ. max. unit notes ale low to rd low tdar 3 tcp - - 3 tcp + ns 1, 2 rd low to data valid tdda - - 4 tcp ns 1 data hold from rd high tddh 0 - 2 tcp ns data float from rd high tddz 0 - 2 tcp ns rd pulse width tdrd 6 tcp - 6 tcp - ns 2 note s: 1. data memory acc e s s time is 8 tcp. 2. " " (due to buffer drivin g delay and wire loadin g ) is 20 ns. 20.3.4 data write c y cle parameter symbol min. typ. max. unit
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 73 - revision a10 ale low to wr low tdaw 3 tcp - - 3 tcp + ns data valid to wr low tdad 1 tcp - - - ns data hold from wr high tdwd 1 tcp - - - ns wr pulse width tdwr 6 tcp - 6 tcp - ns note: " " (du e to buffer dri v ing delay an d wire lo adin g ) is 20 ns. 20.3.5 port acces s c y cl e parameter symbol min. typ. max. unit port input setup to ale low tpds 1 tcp - - ns port input hold from ale low tpdh 0 - - ns port output to ale tpda 1 tcp - - ns note: ports a r e re ad du rin g s5p2, and output data b e com e s avail able at the en d of s6p2. the timing data are referenced to ale, since it provides a conve n ient referen c e . 20.3.6 program operation parameter symbol min. typ. max. unit vpp setup time tvps 2.0 - - s data setup ti me tds 2.0 - - s data h old ti me tdh 2.0 - - s addre s s setup time tas 2.0 - - s addre s s hol d time tah 0 - - s ce progra m pulse wi dth for pro- gram o peration tpwp 290 300 310 s oect rl set up time tocs 2.0 - - s oect rl h ol d time toc h 2.0 - - s oe setup time toes 2.0 - - s oe high to outp ut float tdfp 0 - 130 ns data valid from oe toev - - 150 ns note: flash data can be accessed only in flash mode. the rst pin must pull in vih status, the ale pin must pull in vil status, and the psen pin must pull in vih status.
w78e054d/w78e052d/W78E051D data sheet - 74 - 20.4 timing w a veforms 20.4.1 program fe tch c y cle s1 xtal1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 ale port 2 a0-a7 a0-a7 data a0-a7 code t a0-a7 data code port 0 psen pdh, t pdz t pda t aah t aas t psw t apl t alw 20.4.2 data r ead c y cle s2 s3 s5 s6 s1 s2 s3 s4 s1 s5 s6 s4 xtal1 ale psen a8-a15 data out port 2 port 0 a0-a7 wr t t daw dad t dwr t dwd
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 75 - revision a10 20.4.3 data write c y cle s2 s3 s5 s6 s1 s2 s3 s4 s1 s5 s6 s4 xtal1 ale psen a8-a15 data out port 2 port 0 a0-a7 wr t t daw dad t dwr t dwd 20.4.4 port acces s c y cl e xtal1 ale s5 s6 s1 data out t t port input t sample pda pdh pds
w78e054d/w78e052d/W78E051D data sheet - 76 - 20.4.5 rese t pin a cces s c y cle v ss v dd pof internal reset powe r 1 = r e set state 0 = cpu fr ee ru nni n g ~0 .7v reset pi n ale crystal clock 65 536 crystal clo c k ~2.0v 12 crystal clo c k = 1 machine cycle 24 crystal clo c k
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 77 - revision a10 21 applicat ion circuits 21.1 external program memor y and cr y s tal a9 a11 psen a1 vcc ad2 rs t a8 r a3 a13 a12 c2 64kb rom 10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 1 20 22 11 12 13 15 16 17 18 19 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 ce oe o0 o1 o2 o3 o4 o5 o6 o7 ad 5 ad5 ad4 c1 ad7 ad3 a1 0 ad1 74373 3 2 4 5 7 6 8 9 13 12 14 15 17 16 18 19 1 11 d0 q0 d1 q 1 d2 q 2 d3 q 3 d4 q 4 d5 q 5 d6 q 6 d7 q 7 oc g ad 2 a15 a14 ad1 a7 ale a4 crystal a11 vc c ad5 a6 a2 a0 ad 6 ad4 a12 w78e054ddg-40dip 31 19 18 9 12 13 14 15 1 2 3 4 5 6 7 8 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10 20 40 ea xt a l 1 xt a l 2 rs t p3.2/int0 p3.3/int1 p 3 .4 /t 0 p 3 .5 /t 1 p 1 .0 /t 2 p 1 .1 /t 2 e x p1. 2 p1. 3 p1. 4 p1. 5 p1. 6 p1. 7 p0 . 0 p0 . 1 p0 . 2 p0 . 3 p0 . 4 p0 . 5 p0 . 6 p0 . 7 p2 . 0 p2 . 1 p2 . 2 p2 . 3 p2 . 4 p2 . 5 p2 . 6 p2 . 7 rd/p3.7 wr/p3.6 psen ale tx d / p 3 . 1 rx d/p 3 .0 vss vdd a8 a5 a1 a6 w78e052ddg-40dip W78E051Ddg-40dip a4 10uf a0 ad7 a2 ad2 ad3 a1 5 a1 4 a3 a10 ad7 a9 ad 6 ad1 ad0 a5 a13 ad4 ad6 ad 3 ad0 8.2k a7 ad0 figure a 21.2 expanded external data memory a nd oscillator 64kb ram 12 11 10 9 8 7 6 5 27 26 23 25 4 28 3 31 13 14 15 17 18 19 20 21 22 30 24 29 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a1 0 a1 1 a1 2 a1 3 a1 4 a1 5 d0 d1 d2 d3 d4 d5 d6 d7 cs 1 cs2 oe we ad7 a13 a10 ad4 a1 2 a7 8.2k a15 a13 ad2 a5 a6 10uf a1 ad 5 a8 a3 a2 ale ad6 ad 1 a12 a15 a4 a8 a5 vc c rs t ad 0 a10 ad1 a4 ad1 ad 6 /w r vc c ad7 a14 ad6 74373 3 2 4 5 7 6 8 9 13 12 14 15 17 16 18 19 1 11 d0 q0 d1 q 1 d2 q 2 d3 q 3 d4 q 4 d5 q 5 d6 q 6 d7 q 7 oc g w78e052ddg-40dip W78E051Ddg-40dip a14 vcc ad5 a6 ad 2 ad 4 a7 a2 ad 4 /rd ad5 a9 ad7 ad3 a0 a11 a9 a1 os c i l l at or a0 ad3 vcc ad 0 a11 ad3 ad 2 a3 ad0 w78e054ddg-40dip 31 19 18 9 12 13 14 15 1 2 3 4 5 6 7 8 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10 20 40 ea xt a l 1 xt a l 2 rs t p3.2/int0 p3.3/int1 p 3 .4 /t 0 p 3 .5 /t 1 p 1 .0 /t 2 p 1 .1 /t 2 e x p1 . 2 p1 . 3 p1 . 4 p1 . 5 p1 . 6 p1 . 7 p0 . 0 p0 . 1 p0 . 2 p0 . 3 p0 . 4 p0 . 5 p0 . 6 p0 . 7 p2 . 0 p2 . 1 p2 . 2 p2 . 3 p2 . 4 p2 . 5 p2 . 6 p2 . 7 rd/p3.7 wr/p3.6 psen ale tx d / p 3 . 1 rx d/ p 3 . 0 vss vdd figure b
w78e054d/w78e052d/W78E051D data sheet - 78 - 21.3 internal program memor y and oscillator for eft application ad6 ad4 a12 ad5 8.2k ad4 10uf ad7 a3 ad1 vcc a9 ad5 ad0 a6 ad2 a15 a15 a0 a0 a6 a12 ad3 a10 rst a1 a9 a5 ad2 a11 ad3 w78e054ddg-40dip ea 31 xta l 1 19 xta l 2 18 rst 9 p3.2/int0 12 p3.3/int1 13 p3.4/t0 14 p3.5/t1 15 p1.0/t2 1 p1.1/t2ex 2 p1.2 3 p1.3 4 p1.4 5 p1.5 6 p1.6 7 p1.7 8 p0.0 39 p0.1 38 p0.2 37 p0.3 36 p0.4 35 p0.5 34 p0.6 33 p0.7 32 p2.0 21 p2.1 22 p2.2 23 p2. 3 24 p2.4 25 p2.5 26 p2.6 27 p2.7 28 rd/p3.7 17 wr/p3.6 16 psen 29 ale 30 txd / p3. 1 11 rxd/p3.0 10 vss 20 vdd 40 a4 ad5 ad0 ad3 ad1 a13 ad7 a1 a8 ad7 ale a11 ad1 ad6 a2 a10 74373 d0 3 q0 2 d1 4 q1 5 d2 7 q2 6 d3 8 q3 9 d4 13 q4 12 d5 14 q5 15 d6 17 q6 16 d7 18 q7 19 oc 1 g 11 ad4 a14 ad0 a14 a5 a13 a3 a7 a7 a8 ad6 vcc a2 ad2 a4 64kb ram a0 12 a1 11 a2 10 a3 9 a4 8 a5 7 a6 6 a7 5 a8 27 a9 26 a10 23 a11 25 a12 4 a13 28 a14 3 a15 31 d0 13 d1 14 d2 15 d3 17 d4 18 d5 19 d6 20 d7 21 cs1 22 cs2 30 oe 24 we 29 /wr /rd vcc w78e052ddg-40dip W78E051Ddg-40dip cry stal r c2 c1 10k figure c 21.4 ref e ren ce value of xtal crystal c1 c2 r 6 mhz 68p 68p - 16 mhz 47p 47p - 24 mhz 20p 20p - 32 mhz 10p 10p 6.8k 40 mhz 5p 5p 4.7k above table show s the refe rence value s for c r y s t a l a pp l i c at i o ns . not e s : 1 . c1 , c2 , r c omponents r e fer to figu re a , c 2 . c r y stal la y ou t m ust ge t clo s e to xt al1 and xt al2 pin s on u s er' s app lica t i on board .
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 79 - revision a10 22 application note in-s y s tem programming soft w a re ex amples this application note illust rates the in-sy s tem programmability of the mi crocontroller. in this example, microcontroll er will boot from 2k ldro m bank ente r in-system p r ogra mming mode for pro grammi ng the content s of aprom, this sa mple to erase ap rom, era s e verify apr om, read o ne byte for aprom, writ e one byte for aprom, re ad cid/ did. . example: base on keil c51 compiler $nomod51 #include eapage data 0beh chpcon data 0bfh sfral data 0c4h sfrah data 0c5h sfrfd data 0c6h sfrcn data 0c7h ;cpu clock = 12mhz/12t mode read_time equ 1 program_time equ 50 erase_time equ 5000 ;for w78e(i)054d aprom_end_address equ 03800h ;for w78e(i)052d ;aprom_end_address equ 02000h ;for w78e(i)051d ;aprom_end_address equ 01000h flash_standby equ 00111111b read_cid equ 00001011b read_did equ 00001100b erase_rom equ 00100010b erase_verify equ 00001001b program_rom equ 00100001b program_verify_rom equ 00001010b read_rom equ 00000000b org 03800h mov sp,#060h
w78e054d/w78e052d/W78E051D data sheet - 80 - mov tmod,#01h ;set timer0 as mode1 call read_company_id call read_device_id_high call read_device_id_low call erase_aprom call erase_verify_rom call program_aprom call program_verify_aprom call software_reset sjmp $ ;************************************************************************ ; * read_company_id ;************************************************************************ read_company_id: mov sfrcn,#read_cid mov tl0,#low (65536-read_time) mov th0,#high(65536-read_time) setb tr0 mov chpcon,#00000011b clr tf0 clr tr0 mov a,sfrfd ;check read company id cjne a,#0dah,cid_error ret cid_error: mov p1,#01h sjmp $ ;************************************************************************ ; * read device id high ;************************************************************************ read_device_id_high: mov sfral,#0ffh mov sfrah,#0ffh mov sfrcn,#read_did mov tl0,#low (65536-read_time) mov th0,#high(65536-read_time) setb tr0 mov chpcon,#00000011b clr tf0 clr tr0 mov a,sfrfd ;read device id high byte ret ;************************************************************************* ; * read device id low
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 81 - revision a10 ;************************************************************************* read_device_id_low: mov sfral,#0feh mov sfrah,#0ffh mov sfrcn,#read_did mov tl0,#low (65536-read_time) mov th0,#high(65536-read_time) setb tr0 mov chpcon,#00000011b clr tf0 clr tr0 mov a,sfrfd ;read device id low byte ret ;************************************************************************ ;* flash standby mode ;************************************************************************ standby: mov sfrcn,#flash_standby mov sfrfd,#0ffh mov sfral,#0ffh mov sfrah,#0ffh setb tr0 mov chpcon,#00000011b clr tf0 clr tr0 ret ;************************************************************************ ;* erase aprom ;************************************************************************ erase_aprom: mov eapage,#01h ;set eapage is aprom mov sfrcn,#erase_rom mov tl0,#low (65536-erase_time) mov th0,#high(65536-erase_time) setb tr0 mov chpcon,#00000011b mov eapage,#00h ;clear eapage clr tf0 clr tr0 ret ;************************************************************************ ; * verify aprom bank ;************************************************************************
w78e054d/w78e052d/W78E051D data sheet - 82 - erase_verify_rom: mov sfrcn,#erase_verify mov dptr,#0000h er_lp: mov tl0,#low (65536-read_time) mov th0,#high(65536-read_time) mov sfral,dpl mov sfrah,dph setb tr0 mov chpcon,#00000011b clr tf0 clr tr0 mov a,sfrfd cjne a,#0ffh,erase_verify_error inc dptr mov r0,dpl cjne r0,#low (aprom_end_address),er_lp mov r1,dph cjne r1,#high(aprom_end_address),er_lp ret erase_verify_error: mov p1,#02h sjmp $ ;************************************************************************** ;*programming aprom bank, aprom write 55h,aah,55h,aah........ ;************************************************************************** program_aprom: mov sfrcn,#program_rom mov dptr,#0000h mov a,#055h wr_lp: mov th0,#high(65536-program_time) mov tl0,#low (65536-program_time) mov sfrfd,a mov sfral,dpl mov sfrah,dph setb tr0 mov chpcon,#00000011b clr tf0 clr tr0 cpl a inc dptr mov r0,dpl cjne r0,#low (aprom_end_address),wr_lp
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 83 - revision a10 mov r1,dph cjne r1,#high(aprom_end_address),wr_lp ret ;************************************************************************** ;*program verify aprom bank, read aprom 55h,aah,55h,aah........ ;************************************************************************** program_verify_aprom: mov sfrcn,#program_verify_rom mov dptr,#0000h mov b,#055h rd_lp: mov th0,#high(65536-read_time) mov tl0,#low (65536-read_time) mov sfral,dpl mov sfrah,dph setb tr0 mov chpcon,#00000011b clr tf0 clr tr0 mov a,sfrfd cjne a,b,program_fail mov a,b cpl a mov b,a inc dptr mov r0,dpl cjne r0,#low (aprom_end_address),rd_lp mov r1,dph cjne r1,#high(aprom_end_address),rd_lp ret program_fail: mov p1,#03h sjmp $ ;************************************************************************** ;* programming completly, software reset cpu to aprom ;************************************************************************** software_reset: mov chpcon,#081h ;chpcon=081h, software reset to aprom. sjmp $ end
w78e054d/w78e052d/W78E051D data sheet - 84 - 23 package dimensions 23.1 40-pin dip 1.37 1.22 0.054 0.048 symbol min nom max max nom min dimension in inch dimension in mm a b c d e a l s a a 1 2 e 0.050 1.27 0.210 5.33 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.41 0.25 3.94 0.46 4.06 0.56 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.20 3.05 0.25 3.30 0.36 3.56 0.540 0.550 0.545 13.72 13.97 13.84 17.02 15.24 14.99 15.49 0.600 0.590 0.610 2.29 2.54 2.79 0.090 0.100 0.110 b 1 1 e e 1 2.055 2.070 52.20 52.58 01 5 0.090 2.29 0.650 0.630 16.00 16.51 15 0 seating plane e a 2 a c e base plane 1 a 1 e l a s 1 e d 1 b b 40 21 20 1
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 85 - revision a10 23.2 44-pin plcc 44 40 39 29 28 18 17 7 61 l c 1 b 2 a h d d e b eh e y a a 1 seating plane d g g e symbol min nom max max nom min dimension in inch dimension in mm a b c d e h e l y a a 1 2 e b 1 h d g g d e 0.020 0.145 0.026 0.016 0.008 0.648 0.590 0.680 0.090 0.150 0.028 0.018 0.010 0.653 0.610 0.690 0.100 0.050 bsc 0.185 0.155 0.032 0.022 0.014 0.658 0.630 0.700 0.110 0.004 0.51 3.68 0.66 0.41 0.20 16.46 14.99 17.27 2.29 3.81 0.71 0.46 0.25 16.59 15.49 17.53 2.54 1.27 4.70 3.94 0.81 0.56 0.36 16.71 16.00 17.78 2.79 0.10 bsc 16.71 16.59 16.46 0.658 0.653 0.648 16.00 15.49 14.99 0.630 0.610 0.590 17.78 17.53 17.27 0.700 0.690 0.680
w78e054d/w78e052d/W78E051D data sheet - 86 - 23.3 44-pin pqfp 0.25 0.10 0.010 0.004 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y 0 a a l 1 1 2 e 0.006 0.15 - - 0.002 0.075 0.01 0.081 0.014 0.087 0.018 1.90 0.25 0.05 2.05 0.35 2.20 0.45 0.390 0.510 0.025 0.063 0.004 0 10 0.394 0.520 0.031 0.398 0.530 0.037 9.9 0.80 12.95 0.65 1.60 10.00 13.20 0.8 10.1 13.45 0.95 0.398 0.394 0.390 0.530 0.520 0.510 13.45 13.20 12.95 10.1 10.00 9.9 10 0 0.10 .0315 0.01 0.02 0.25 0.5 seating plane 11 22 12 see detail f e b a y 1 a a 2 l l 1 c e e h 1 d 44 h d 34 33 detail f
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 87 - revision a10 23.4 48-pin lqfp
w78e054d/w78e052d/W78E051D data sheet - 88 - 24 revision history versio n date pag e descri ptio n a01 august 14, 2008 - initial issued a02 nov emb er 3,2008 - update dc table typing error. a03 de cemb er 15,200 8 - update config bit table, and isp boot a04 jan uary 7,2007 70 update v il and v ih . a05 march 9, 200 9 43 update soft reset, only ld jump to ap function. a06 march 20, 2009 18 - - 1. renam e sfr re giste r por (0x8 6h) to p0upr. 2. revis e s o me typing errors in data s h eet. 3. update dc table a07 april 22, 200 9 68 1. revise type application circuit in data sheet. a08 jun e 30, 200 9 30 61 81 all pages 1. add the isp control table. 2. revise co nte n t of char. 17 . 3. modify the isp demo co de . 4. remove the ?preliminary? character for each page. a09 de c 30, 200 9 68 77 1. revise the ?config bits? desc r iption for bit4, bit6 and bit7. 2. add the timing for external reset pin. a10 oct 20, 201 1 28 70 1. revised the chp co n de scription 2. added de scri ption for ?2 1.4 referen c e value of xtal
w78e054d/w78e052d/W78E051D data sheet pub lica tio n relea s e da te: oct 2 0 , 2 011 - 89 - revision a10 important notice nuv oton products are ne ither inten de d nor w a rra n t ed fo r usag e in s y stems or equipment, an y malfunc tion or failure of w h i c h ma y c a use loss o f human life, bodily injur y or sev ere pr operty damage. su ch applicatio ns are deem ed, ?insec ur e usag e?. insecure u s a ge includes, but is not limited to: e q uipment for surgical implementa tion, atomic energ y contr ol instrumen t s, airplane or space shi p instruments, the control or operation of d y - namic, brake or safe t y s y stems de sig ned for v e hicu lar use, tr affic sign al instrume nts, all t y pes of sa fety de v i ces, and oth e r applicatio ns intend ed to suppo rt o r sustain life . all insecur e usa ge sh all be made a t cus t omer?s risk, and in the ev ent that third pa rties la y claims to nuv oton as a result of c ustomer?s in secur e usa ge, cus t ome r shall inde mnif y th e damages and liabilities thus incurred b y nu v o ton.

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